forked from Minki/linux
i40e: clear all queues and interrupts
Per a recent HW designer comment, this code is for ripping through the queues and interrupts to fully disable them on driver init, specifically to help clean up after a PXE or other early boot activity. Change-ID: I32ed452021a1c2b06dace1969976f882a37b9741 Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -810,6 +810,99 @@ i40e_status i40e_pf_reset(struct i40e_hw *hw)
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return 0;
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}
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/**
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* i40e_clear_hw - clear out any left over hw state
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* @hw: pointer to the hw struct
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*
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* Clear queues and interrupts, typically called at init time,
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* but after the capabilities have been found so we know how many
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* queues and msix vectors have been allocated.
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**/
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void i40e_clear_hw(struct i40e_hw *hw)
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{
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u32 num_queues, base_queue;
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u32 num_pf_int;
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u32 num_vf_int;
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u32 num_vfs;
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u32 i, j;
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u32 val;
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u32 eol = 0x7ff;
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/* get number of interrupts, queues, and vfs */
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val = rd32(hw, I40E_GLPCI_CNF2);
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num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
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I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
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num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
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I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
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val = rd32(hw, I40E_PFLAN_QALLOC);
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base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
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I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
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j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
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I40E_PFLAN_QALLOC_LASTQ_SHIFT;
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if (val & I40E_PFLAN_QALLOC_VALID_MASK)
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num_queues = (j - base_queue) + 1;
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else
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num_queues = 0;
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val = rd32(hw, I40E_PF_VT_PFALLOC);
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i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
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I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
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j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
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I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
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if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
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num_vfs = (j - i) + 1;
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else
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num_vfs = 0;
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/* stop all the interrupts */
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wr32(hw, I40E_PFINT_ICR0_ENA, 0);
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val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
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for (i = 0; i < num_pf_int - 2; i++)
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wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
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/* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
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val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
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wr32(hw, I40E_PFINT_LNKLST0, val);
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for (i = 0; i < num_pf_int - 2; i++)
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wr32(hw, I40E_PFINT_LNKLSTN(i), val);
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val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
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for (i = 0; i < num_vfs; i++)
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wr32(hw, I40E_VPINT_LNKLST0(i), val);
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for (i = 0; i < num_vf_int - 2; i++)
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wr32(hw, I40E_VPINT_LNKLSTN(i), val);
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/* warn the HW of the coming Tx disables */
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for (i = 0; i < num_queues; i++) {
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u32 abs_queue_idx = base_queue + i;
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u32 reg_block = 0;
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if (abs_queue_idx >= 128) {
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reg_block = abs_queue_idx / 128;
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abs_queue_idx %= 128;
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}
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val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
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val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
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val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
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val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
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wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
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}
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udelay(400);
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/* stop all the queues */
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for (i = 0; i < num_queues; i++) {
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wr32(hw, I40E_QINT_TQCTL(i), 0);
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wr32(hw, I40E_QTX_ENA(i), 0);
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wr32(hw, I40E_QINT_RQCTL(i), 0);
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wr32(hw, I40E_QRX_ENA(i), 0);
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}
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/* short wait for all queue disables to settle */
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udelay(50);
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}
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/**
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* i40e_clear_pxe_mode - clear pxe operations mode
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* @hw: pointer to the hw struct
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@ -8636,6 +8636,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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/* Reset here to make sure all is clean and to define PF 'n' */
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i40e_clear_hw(hw);
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err = i40e_pf_reset(hw);
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if (err) {
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dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
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@ -217,6 +217,7 @@ i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
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/* i40e_common */
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i40e_status i40e_init_shared_code(struct i40e_hw *hw);
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i40e_status i40e_pf_reset(struct i40e_hw *hw);
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void i40e_clear_hw(struct i40e_hw *hw);
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void i40e_clear_pxe_mode(struct i40e_hw *hw);
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bool i40e_get_link_status(struct i40e_hw *hw);
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i40e_status i40e_get_mac_addr(struct i40e_hw *hw,
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