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drm/nouveau: pass handle of vmm object to channel allocation ioctls

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2017-11-01 03:56:20 +10:00
parent 3c5026395b
commit 832ca2ac3c
17 changed files with 54 additions and 41 deletions
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2
drivers/gpu/drm/nouveau/include/nvif/cl506e.h
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@ -5,7 +5,7 @@ struct nv50_channel_dma_v0 {
__u8 version; __u8 version;
__u8 chid; __u8 chid;
__u8 pad02[6]; __u8 pad02[6];
__u64 vm; __u64 vmm;
__u64 pushbuf; __u64 pushbuf;
__u64 offset; __u64 offset;
}; };

2
drivers/gpu/drm/nouveau/include/nvif/cl506f.h
View File

@ -8,6 +8,6 @@ struct nv50_channel_gpfifo_v0 {
__u32 ilength; __u32 ilength;
__u64 ioffset; __u64 ioffset;
__u64 pushbuf; __u64 pushbuf;
__u64 vm; __u64 vmm;
}; };
#endif #endif

2
drivers/gpu/drm/nouveau/include/nvif/cl826e.h
View File

@ -5,7 +5,7 @@ struct g82_channel_dma_v0 {
__u8 version; __u8 version;
__u8 chid; __u8 chid;
__u8 pad02[6]; __u8 pad02[6];
__u64 vm; __u64 vmm;
__u64 pushbuf; __u64 pushbuf;
__u64 offset; __u64 offset;
}; };

2
drivers/gpu/drm/nouveau/include/nvif/cl826f.h
View File

@ -8,7 +8,7 @@ struct g82_channel_gpfifo_v0 {
__u32 ilength; __u32 ilength;
__u64 ioffset; __u64 ioffset;
__u64 pushbuf; __u64 pushbuf;
__u64 vm; __u64 vmm;
}; };
#define NV826F_V0_NTFY_NON_STALL_INTERRUPT 0x00 #define NV826F_V0_NTFY_NON_STALL_INTERRUPT 0x00

2
drivers/gpu/drm/nouveau/include/nvif/cl906f.h
View File

@ -7,7 +7,7 @@ struct fermi_channel_gpfifo_v0 {
__u8 pad02[2]; __u8 pad02[2];
__u32 ilength; __u32 ilength;
__u64 ioffset; __u64 ioffset;
__u64 vm; __u64 vmm;
}; };
#define NV906F_V0_NTFY_NON_STALL_INTERRUPT 0x00 #define NV906F_V0_NTFY_NON_STALL_INTERRUPT 0x00

2
drivers/gpu/drm/nouveau/include/nvif/cla06f.h
View File

@ -22,7 +22,7 @@ struct kepler_channel_gpfifo_a_v0 {
__u32 engines; __u32 engines;
__u32 ilength; __u32 ilength;
__u64 ioffset; __u64 ioffset;
__u64 vm; __u64 vmm;
}; };
#define NVA06F_V0_NTFY_NON_STALL_INTERRUPT 0x00 #define NVA06F_V0_NTFY_NON_STALL_INTERRUPT 0x00

7
drivers/gpu/drm/nouveau/nouveau_chan.c
View File

@ -205,6 +205,7 @@ static int
nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
u32 engine, struct nouveau_channel **pchan) u32 engine, struct nouveau_channel **pchan)
{ {
struct nouveau_cli *cli = (void *)device->object.client;
static const u16 oclasses[] = { PASCAL_CHANNEL_GPFIFO_A, static const u16 oclasses[] = { PASCAL_CHANNEL_GPFIFO_A,
MAXWELL_CHANNEL_GPFIFO_A, MAXWELL_CHANNEL_GPFIFO_A,
KEPLER_CHANNEL_GPFIFO_B, KEPLER_CHANNEL_GPFIFO_B,
@ -236,21 +237,21 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
args.kepler.engines = engine; args.kepler.engines = engine;
args.kepler.ilength = 0x02000; args.kepler.ilength = 0x02000;
args.kepler.ioffset = 0x10000 + chan->push.addr; args.kepler.ioffset = 0x10000 + chan->push.addr;
args.kepler.vm = 0; args.kepler.vmm = nvif_handle(&cli->vmm.vmm.object);
size = sizeof(args.kepler); size = sizeof(args.kepler);
} else } else
if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
args.fermi.version = 0; args.fermi.version = 0;
args.fermi.ilength = 0x02000; args.fermi.ilength = 0x02000;
args.fermi.ioffset = 0x10000 + chan->push.addr; args.fermi.ioffset = 0x10000 + chan->push.addr;
args.fermi.vm = 0; args.fermi.vmm = nvif_handle(&cli->vmm.vmm.object);
size = sizeof(args.fermi); size = sizeof(args.fermi);
} else { } else {
args.nv50.version = 0; args.nv50.version = 0;
args.nv50.ilength = 0x02000; args.nv50.ilength = 0x02000;
args.nv50.ioffset = 0x10000 + chan->push.addr; args.nv50.ioffset = 0x10000 + chan->push.addr;
args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
args.nv50.vm = 0; args.nv50.vmm = nvif_handle(&cli->vmm.vmm.object);
size = sizeof(args.nv50); size = sizeof(args.nv50);
} }

12
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
View File

@ -27,7 +27,6 @@
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <core/oproxy.h> #include <core/oproxy.h>
#include <subdev/mmu.h> #include <subdev/mmu.h>
#include <subdev/mmu/priv.h>
#include <engine/dma.h> #include <engine/dma.h>
struct nvkm_fifo_chan_object { struct nvkm_fifo_chan_object {
@ -353,8 +352,8 @@ nvkm_fifo_chan_func = {
int int
nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func,
struct nvkm_fifo *fifo, u32 size, u32 align, bool zero, struct nvkm_fifo *fifo, u32 size, u32 align, bool zero,
u64 vm, u64 push, u64 engines, int bar, u32 base, u32 user, u64 hvmm, u64 push, u64 engines, int bar, u32 base,
const struct nvkm_oclass *oclass, u32 user, const struct nvkm_oclass *oclass,
struct nvkm_fifo_chan *chan) struct nvkm_fifo_chan *chan)
{ {
struct nvkm_client *client = oclass->client; struct nvkm_client *client = oclass->client;
@ -387,8 +386,11 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func,
} }
/* channel address space */ /* channel address space */
if (!device->mmu->func->vmm.global) { if (hvmm) {
struct nvkm_vmm *vmm = client->vm; struct nvkm_vmm *vmm = nvkm_uvmm_search(client, hvmm);
if (IS_ERR(vmm))
return PTR_ERR(vmm);
if (vmm->mmu != device->mmu) if (vmm->mmu != device->mmu)
return -EINVAL; return -EINVAL;

7
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
View File

@ -229,15 +229,18 @@ g84_fifo_chan_func = {
}; };
int int
g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push, g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vmm, u64 push,
const struct nvkm_oclass *oclass, const struct nvkm_oclass *oclass,
struct nv50_fifo_chan *chan) struct nv50_fifo_chan *chan)
{ {
struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_device *device = fifo->base.engine.subdev.device;
int ret; int ret;
if (!vmm)
return -EINVAL;
ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base, ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base,
0x10000, 0x1000, false, vm, push, 0x10000, 0x1000, false, vmm, push,
(1ULL << NVKM_ENGINE_BSP) | (1ULL << NVKM_ENGINE_BSP) |
(1ULL << NVKM_ENGINE_CE0) | (1ULL << NVKM_ENGINE_CE0) |
(1ULL << NVKM_ENGINE_CIPHER) | (1ULL << NVKM_ENGINE_CIPHER) |

7
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
View File

@ -228,15 +228,18 @@ nv50_fifo_chan_func = {
}; };
int int
nv50_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push, nv50_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vmm, u64 push,
const struct nvkm_oclass *oclass, const struct nvkm_oclass *oclass,
struct nv50_fifo_chan *chan) struct nv50_fifo_chan *chan)
{ {
struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_device *device = fifo->base.engine.subdev.device;
int ret; int ret;
if (!vmm)
return -EINVAL;
ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base, ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base,
0x10000, 0x1000, false, vm, push, 0x10000, 0x1000, false, vmm, push,
(1ULL << NVKM_ENGINE_DMAOBJ) | (1ULL << NVKM_ENGINE_DMAOBJ) |
(1ULL << NVKM_ENGINE_SW) | (1ULL << NVKM_ENGINE_SW) |
(1ULL << NVKM_ENGINE_GR) | (1ULL << NVKM_ENGINE_GR) |

4
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
View File

@ -17,14 +17,14 @@ struct nv50_fifo_chan {
struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR];
}; };
int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push, int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push,
const struct nvkm_oclass *, struct nv50_fifo_chan *); const struct nvkm_oclass *, struct nv50_fifo_chan *);
void *nv50_fifo_chan_dtor(struct nvkm_fifo_chan *); void *nv50_fifo_chan_dtor(struct nvkm_fifo_chan *);
void nv50_fifo_chan_fini(struct nvkm_fifo_chan *); void nv50_fifo_chan_fini(struct nvkm_fifo_chan *);
void nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *, struct nvkm_engine *); void nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *, struct nvkm_engine *);
void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int); void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int);
int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push, int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push,
const struct nvkm_oclass *, struct nv50_fifo_chan *); const struct nvkm_oclass *, struct nv50_fifo_chan *);
extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass; extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass;

6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c
View File

@ -44,9 +44,9 @@ g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl(parent, "create channel dma size %d\n", size); nvif_ioctl(parent, "create channel dma size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create channel dma vers %d vm %llx " nvif_ioctl(parent, "create channel dma vers %d vmm %llx "
"pushbuf %llx offset %016llx\n", "pushbuf %llx offset %016llx\n",
args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.version, args->v0.vmm, args->v0.pushbuf,
args->v0.offset); args->v0.offset);
if (!args->v0.pushbuf) if (!args->v0.pushbuf)
return -EINVAL; return -EINVAL;
@ -57,7 +57,7 @@ g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return -ENOMEM; return -ENOMEM;
*pobject = &chan->base.object; *pobject = &chan->base.object;
ret = g84_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
oclass, chan); oclass, chan);
if (ret) if (ret)
return ret; return ret;

6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c
View File

@ -44,9 +44,9 @@ nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl(parent, "create channel dma size %d\n", size); nvif_ioctl(parent, "create channel dma size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create channel dma vers %d vm %llx " nvif_ioctl(parent, "create channel dma vers %d vmm %llx "
"pushbuf %llx offset %016llx\n", "pushbuf %llx offset %016llx\n",
args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.version, args->v0.vmm, args->v0.pushbuf,
args->v0.offset); args->v0.offset);
if (!args->v0.pushbuf) if (!args->v0.pushbuf)
return -EINVAL; return -EINVAL;
@ -57,7 +57,7 @@ nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return -ENOMEM; return -ENOMEM;
*pobject = &chan->base.object; *pobject = &chan->base.object;
ret = nv50_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
oclass, chan); oclass, chan);
if (ret) if (ret)
return ret; return ret;

6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c
View File

@ -45,10 +45,10 @@ g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl(parent, "create channel gpfifo size %d\n", size); nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
"pushbuf %llx ioffset %016llx " "pushbuf %llx ioffset %016llx "
"ilength %08x\n", "ilength %08x\n",
args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.version, args->v0.vmm, args->v0.pushbuf,
args->v0.ioffset, args->v0.ilength); args->v0.ioffset, args->v0.ilength);
if (!args->v0.pushbuf) if (!args->v0.pushbuf)
return -EINVAL; return -EINVAL;
@ -59,7 +59,7 @@ g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return -ENOMEM; return -ENOMEM;
*pobject = &chan->base.object; *pobject = &chan->base.object;
ret = g84_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
oclass, chan); oclass, chan);
if (ret) if (ret)
return ret; return ret;

8
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
View File

@ -225,10 +225,12 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl(parent, "create channel gpfifo size %d\n", size); nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
"ioffset %016llx ilength %08x\n", "ioffset %016llx ilength %08x\n",
args->v0.version, args->v0.vm, args->v0.ioffset, args->v0.version, args->v0.vmm, args->v0.ioffset,
args->v0.ilength); args->v0.ilength);
if (!args->v0.vmm)
return -EINVAL;
} else } else
return ret; return ret;
@ -240,7 +242,7 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
INIT_LIST_HEAD(&chan->head); INIT_LIST_HEAD(&chan->head);
ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base, ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base,
0x1000, 0x1000, true, args->v0.vm, 0, 0x1000, 0x1000, true, args->v0.vmm, 0,
(1ULL << NVKM_ENGINE_CE0) | (1ULL << NVKM_ENGINE_CE0) |
(1ULL << NVKM_ENGINE_CE1) | (1ULL << NVKM_ENGINE_CE1) |
(1ULL << NVKM_ENGINE_GR) | (1ULL << NVKM_ENGINE_GR) |

14
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
View File

@ -231,7 +231,7 @@ struct gk104_fifo_chan_func {
static int static int
gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func, gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
struct gk104_fifo *fifo, u32 *engmask, u16 *chid, struct gk104_fifo *fifo, u32 *engmask, u16 *chid,
u64 vm, u64 ioffset, u64 ilength, u64 vmm, u64 ioffset, u64 ilength,
const struct nvkm_oclass *oclass, const struct nvkm_oclass *oclass,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
@ -241,6 +241,9 @@ gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
u64 subdevs = 0; u64 subdevs = 0;
u64 usermem; u64 usermem;
if (!vmm)
return -EINVAL;
/* Determine which downstream engines are present */ /* Determine which downstream engines are present */
for (i = 0; i < fifo->engine_nr; i++) { for (i = 0; i < fifo->engine_nr; i++) {
struct nvkm_engine *engine = fifo->engine[i].engine; struct nvkm_engine *engine = fifo->engine[i].engine;
@ -286,7 +289,7 @@ gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
INIT_LIST_HEAD(&chan->head); INIT_LIST_HEAD(&chan->head);
ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base, ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
0x1000, 0x1000, true, vm, 0, subdevs, 0x1000, 0x1000, true, vmm, 0, subdevs,
1, fifo->user.bar->addr, 0x200, 1, fifo->user.bar->addr, 0x200,
oclass, &chan->base); oclass, &chan->base);
if (ret) if (ret)
@ -358,18 +361,17 @@ gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl(parent, "create channel gpfifo size %d\n", size); nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
"ioffset %016llx ilength %08x engine %08x\n", "ioffset %016llx ilength %08x engine %08x\n",
args->v0.version, args->v0.vm, args->v0.ioffset, args->v0.version, args->v0.vmm, args->v0.ioffset,
args->v0.ilength, args->v0.engines); args->v0.ilength, args->v0.engines);
return gk104_fifo_gpfifo_new_(gk104_fifo_gpfifo, fifo, return gk104_fifo_gpfifo_new_(gk104_fifo_gpfifo, fifo,
&args->v0.engines, &args->v0.engines,
&args->v0.chid, &args->v0.chid,
args->v0.vm, args->v0.vmm,
args->v0.ioffset, args->v0.ioffset,
args->v0.ilength, args->v0.ilength,
oclass, pobject); oclass, pobject);
} }
return ret; return ret;

6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c
View File

@ -45,10 +45,10 @@ nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl(parent, "create channel gpfifo size %d\n", size); nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
"pushbuf %llx ioffset %016llx " "pushbuf %llx ioffset %016llx "
"ilength %08x\n", "ilength %08x\n",
args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.version, args->v0.vmm, args->v0.pushbuf,
args->v0.ioffset, args->v0.ilength); args->v0.ioffset, args->v0.ilength);
if (!args->v0.pushbuf) if (!args->v0.pushbuf)
return -EINVAL; return -EINVAL;
@ -59,7 +59,7 @@ nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return -ENOMEM; return -ENOMEM;
*pobject = &chan->base.object; *pobject = &chan->base.object;
ret = nv50_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
oclass, chan); oclass, chan);
if (ret) if (ret)
return ret; return ret;