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MIPS updates for v5.8:

Browse Source 
- added support for MIPSr5 and P5600 cores
 - converted Loongson PCI driver into a PCI host driver using the generic
   PCI framework
 - added emulation of CPUCFG command for Loogonson64 cpus
 - removed of LASAT, PMC MSP71xx and NEC MARKEINS/EMMA
 - ioremap cleanup
 - fix for a race between two threads faulting the same page
 - various cleanups and fixes
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Merge tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - added support for MIPSr5 and P5600 cores

 - converted Loongson PCI driver into a PCI host driver using the
   generic PCI framework

 - added emulation of CPUCFG command for Loogonson64 cpus

 - removed of LASAT, PMC MSP71xx and NEC MARKEINS/EMMA

 - ioremap cleanup

 - fix for a race between two threads faulting the same page

 - various cleanups and fixes

* tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (143 commits)
  MIPS: ralink: drop ralink_clk_init for mt7621
  MIPS: ralink: bootrom: mark a function as __init to save some memory
  MIPS: Loongson64: Reorder CPUCFG model match arms
  MIPS: Expose Loongson CPUCFG availability via HWCAP
  MIPS: Loongson64: Guard against future cores without CPUCFG
  MIPS: Fix build warning about "PTR_STR" redefinition
  MIPS: Loongson64: Remove not used pci.c
  MIPS: Loongson64: Define PCI_IOBASE
  MIPS: CPU_LOONGSON2EF need software to maintain cache consistency
  MIPS: DTS: Fix build errors used with various configs
  MIPS: Loongson64: select NO_EXCEPT_FILL
  MIPS: Fix IRQ tracing when call handle_fpe() and handle_msa_fpe()
  MIPS: mm: add page valid judgement in function pte_modify
  mm/memory.c: Add memory read privilege on page fault handling
  mm/memory.c: Update local TLB if PTE entry exists
  MIPS: Do not flush tlb page when updating PTE entry
  MIPS: ingenic: Default to a generic board
  MIPS: ingenic: Add support for GCW Zero prototype
  MIPS: ingenic: DTS: Add memory info of GCW Zero
  MIPS: Loongson64: Switch to generic PCI driver
  ...
This commit is contained in:
Linus Torvalds 2020-06-03 13:32:21 -07:00
commit 8226f11318
333 changed files with 4676 additions and 13059 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
Documentation/devicetree/bindings/mips/loongson/rs780e-acpi.yaml Normal file
View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Loongson RS780E PCH ACPI Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description: |
This controller can be found in Loongson-3 systems with RS780E PCH.
properties:
compatible:
const: loongson,rs780e-acpi
reg:
maxItems: 1
required:
- compatible
- reg
examples:
- |
isa@0 {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0 0x1000>;
acpi@800 {
compatible = "loongson,rs780e-acpi";
reg = <1 0x800 0x100>;
};
};
...

62
Documentation/devicetree/bindings/pci/loongson.yaml Normal file
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@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/loongson.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson PCI Host Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description: |+
PCI host controller found on Loongson PCHs and SoCs.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
oneOf:
- const: loongson,ls2k-pci
- const: loongson,ls7a-pci
- const: loongson,rs780e-pci
reg:
minItems: 1
maxItems: 2
items:
- description: CFG0 standard config space register
- description: CFG1 extended config space register
ranges:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- ranges
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie@1a000000 {
compatible = "loongson,rs780e-pci";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
// CPU_PHYSICAL(2) SIZE(2)
reg = <0x0 0x1a000000 0x0 0x2000000>;
// BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
};
};
...

2
arch/mips/Kbuild
View File

@ -12,7 +12,7 @@ obj-y := $(platform-y)
# make clean traverses $(obj-) without having included .config, so
# everything ends up here
obj- := $(platform-)
obj- := $(platform-y)
# mips object files
# The object files are linked as core-y files would be linked

76
arch/mips/Kbuild.platforms
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@ -1,42 +1,44 @@
# SPDX-License-Identifier: GPL-2.0
# All platforms listed in alphabetic order
platforms += alchemy
platforms += ar7
platforms += ath25
platforms += ath79
platforms += bcm47xx
platforms += bcm63xx
platforms += bmips
platforms += cavium-octeon
platforms += cobalt
platforms += dec
platforms += emma
platforms += generic
platforms += jazz
platforms += jz4740
platforms += lantiq
platforms += lasat
platforms += loongson2ef
platforms += loongson32
platforms += loongson64
platforms += mti-malta
platforms += netlogic
platforms += paravirt
platforms += pic32
platforms += pistachio
platforms += pmcs-msp71xx
platforms += pnx833x
platforms += ralink
platforms += rb532
platforms += sgi-ip22
platforms += sgi-ip27
platforms += sgi-ip30
platforms += sgi-ip32
platforms += sibyte
platforms += sni
platforms += txx9
platforms += vr41xx
platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/
platform-$(CONFIG_AR7) += ar7/
platform-$(CONFIG_ATH25) += ath25/
platform-$(CONFIG_ATH79) += ath79/
platform-$(CONFIG_BCM47XX) += bcm47xx/
platform-$(CONFIG_BCM63XX) += bcm63xx/
platform-$(CONFIG_BMIPS_GENERIC) += bmips/
platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
platform-$(CONFIG_MIPS_COBALT) += cobalt/
platform-$(CONFIG_MACH_DECSTATION) += dec/
platform-$(CONFIG_MIPS_GENERIC) += generic/
platform-$(CONFIG_MACH_JAZZ) += jazz/
platform-$(CONFIG_MACH_INGENIC) += jz4740/
platform-$(CONFIG_LANTIQ) += lantiq/
platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/
platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
platform-$(CONFIG_MACH_LOONGSON64) += loongson64/
platform-$(CONFIG_MIPS_MALTA) += mti-malta/
platform-$(CONFIG_NLM_COMMON) += netlogic/
platform-$(CONFIG_MIPS_PARAVIRT) += paravirt/
platform-$(CONFIG_PIC32MZDA) += pic32/
platform-$(CONFIG_MACH_PISTACHIO) += pistachio/
platform-$(CONFIG_SOC_PNX833X) += pnx833x/
platform-$(CONFIG_RALINK) += ralink/
platform-$(CONFIG_MIKROTIK_RB532) += rb532/
platform-$(CONFIG_SGI_IP22) += sgi-ip22/
platform-$(CONFIG_SGI_IP27) += sgi-ip27/
platform-$(CONFIG_SGI_IP28) += sgi-ip22/
platform-$(CONFIG_SGI_IP30) += sgi-ip30/
platform-$(CONFIG_SGI_IP32) += sgi-ip32/
platform-$(CONFIG_SIBYTE_BCM112X) += sibyte/
platform-$(CONFIG_SIBYTE_SB1250) += sibyte/
platform-$(CONFIG_SIBYTE_BCM1x55) += sibyte/
platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/
platform-$(CONFIG_SNI_RM) += sni/
platform-$(CONFIG_MACH_TX39XX) += txx9/
platform-$(CONFIG_MACH_TX49XX) += txx9/
platform-$(CONFIG_MACH_VR41XX) += vr41xx/
# include the platform specific files
include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platform-y))

174
arch/mips/Kconfig
View File

@ -92,6 +92,9 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select VIRT_TO_BUS
config MIPS_FIXUP_BIGPHYS_ADDR
bool
menu "Machine selection"
choice
@ -157,6 +160,7 @@ config MIPS_ALCHEMY
select CSRC_R4K
select IRQ_MIPS_CPU
select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
select MIPS_FIXUP_BIGPHYS_ADDR if PCI
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
@ -427,23 +431,6 @@ config LANTIQ
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
config LASAT
bool "LASAT Networks platforms"
select CEVT_R4K
select CRC32
select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select HAVE_PCI
select IRQ_MIPS_CPU
select PCI_GT64XXX_PCI0
select MIPS_NILE4
select R5000_CPU_SCACHE
select SYS_HAS_CPU_R5000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
select SYS_SUPPORTS_LITTLE_ENDIAN
config MACH_LOONGSON32
bool "Loongson 32-bit family of machines"
select SYS_SUPPORTS_ZBOOT
@ -475,8 +462,10 @@ config MACH_LOONGSON64
select ISA
select I8259
select IRQ_MIPS_CPU
select NR_CPUS_DEFAULT_4
select NO_EXCEPT_FILL
select NR_CPUS_DEFAULT_64
select USE_GENERIC_EARLY_PRINTK_8250
select PCI_DRIVERS_GENERIC
select SYS_HAS_CPU_LOONGSON64
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_SMP
@ -593,13 +582,6 @@ config MACH_PIC32
Microchip PIC32 is a family of general-purpose 32 bit MIPS core
microcontrollers.
config NEC_MARKEINS
bool "NEC EMMA2RH Mark-eins board"
select SOC_EMMA2RH
select HAVE_PCI
help
This enables support for the NEC Electronics Mark-eins boards.
config MACH_VR41XX
bool "NEC VR4100 series based machines"
select CEVT_R4K
@ -621,30 +603,6 @@ config NXP_STB225
help
Support for NXP Semiconductors STB225 Development Board.
config PMC_MSP
bool "PMC-Sierra MSP chipsets"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select SWAP_IO_SPACE
select NO_EXCEPT_FILL
select BOOT_RAW
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_MIPS16
select IRQ_MIPS_CPU
select SERIAL_8250
select SERIAL_8250_CONSOLE
select USB_EHCI_BIG_ENDIAN_MMIO
select USB_EHCI_BIG_ENDIAN_DESC
help
This adds support for the PMC-Sierra family of Multi-Service
Processor System-On-A-Chips. These parts include a number
of integrated peripherals, interfaces and DSPs in addition to
a variety of MIPS cores.
config RALINK
bool "Ralink based machines"
select CEVT_R4K
@ -1087,10 +1045,8 @@ source "arch/mips/generic/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/jz4740/Kconfig"
source "arch/mips/lantiq/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pic32/Kconfig"
source "arch/mips/pistachio/Kconfig"
source "arch/mips/pmcs-msp71xx/Kconfig"
source "arch/mips/ralink/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
@ -1154,6 +1110,7 @@ config CSRC_IOASIC
bool
config CSRC_R4K
select CLOCKSOURCE_WATCHDOG if CPU_FREQ
bool
config CSRC_SB1250
@ -1211,9 +1168,6 @@ config MIPS_BONITO64
config MIPS_MSC
bool
config MIPS_NILE4
bool
config SYNC_R4K
bool
@ -1334,18 +1288,6 @@ config PCI_XTALK_BRIDGE
config NO_EXCEPT_FILL
bool
config SOC_EMMA2RH
bool
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select SWAP_IO_SPACE
select SYS_HAS_CPU_R5500
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
config SOC_PNX833X
bool
select CEVT_R4K
@ -1419,9 +1361,6 @@ config MIPS_L1_CACHE_SHIFT
default "4" if MIPS_L1_CACHE_SHIFT_4
default "5"
config HAVE_STD_PC_SERIAL_PORT
bool
config ARC_CMDLINE_ONLY
bool
@ -1504,6 +1443,18 @@ config CPU_LOONGSON3_WORKAROUNDS
If unsure, please say Y.
config CPU_LOONGSON3_CPUCFG_EMULATION
bool "Emulate the CPUCFG instruction on older Loongson cores"
default y
depends on CPU_LOONGSON64
help
Loongson-3A R4 and newer have the CPUCFG instruction available for
userland to query CPU capabilities, much like CPUID on x86. This
option provides emulation of the instruction on older Loongson
cores, back to Loongson-3A1000.
If unsure, please say Y.
config CPU_LOONGSON2E
bool "Loongson 2E"
depends on SYS_HAS_CPU_LOONGSON2E
@ -1580,6 +1531,21 @@ config CPU_MIPS32_R2
specific type of processor in your system, choose those that one
otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
config CPU_MIPS32_R5
bool "MIPS32 Release 5"
depends on SYS_HAS_CPU_MIPS32_R5
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_MSA
select HAVE_KVM
select MIPS_O32_FP64_SUPPORT
help
Choose this option to build a kernel for release 5 or later of the
MIPS32 architecture. New MIPS processors, starting with the Warrior
family, are based on a MIPS32r5 processor. If you own an older
processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
config CPU_MIPS32_R6
bool "MIPS32 Release 6"
depends on SYS_HAS_CPU_MIPS32_R6
@ -1632,6 +1598,23 @@ config CPU_MIPS64_R2
specific type of processor in your system, choose those that one
otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
config CPU_MIPS64_R5
bool "MIPS64 Release 5"
depends on SYS_HAS_CPU_MIPS64_R5
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
select CPU_SUPPORTS_MSA
select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
select HAVE_KVM
help
Choose this option to build a kernel for release 5 or later of the
MIPS64 architecture. This is a intermediate MIPS architecture
release partly implementing release 6 features. Though there is no
any hardware known to be based on this release.
config CPU_MIPS64_R6
bool "MIPS64 Release 6"
depends on SYS_HAS_CPU_MIPS64_R6
@ -1650,6 +1633,28 @@ config CPU_MIPS64_R6
family, are based on a MIPS64r6 processor. If you own an older
processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
config CPU_P5600
bool "MIPS Warrior P5600"
depends on SYS_HAS_CPU_P5600
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_MSA
select CPU_SUPPORTS_UNCACHED_ACCELERATED
select CPU_SUPPORTS_CPUFREQ
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select HAVE_KVM
select MIPS_O32_FP64_SUPPORT
help
Choose this option to build a kernel for MIPS Warrior P5600 CPU.
It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
MMU with two-levels TLB, UCA, MSA, MDU core level features and system
level features like up to six P5600 calculation cores, CM2 with L2
cache, IOCU/IOMMU (though might be unused depending on the system-
specific IP core configuration), GIC, CPC, virtualisation module,
eJTAG and PDtrace.
config CPU_R3000
bool "R3000"
depends on SYS_HAS_CPU_R3000
@ -1826,7 +1831,8 @@ endchoice
config CPU_MIPS32_3_5_FEATURES
bool "MIPS32 Release 3.5 Features"
depends on SYS_HAS_CPU_MIPS32_R3_5
depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
CPU_P5600
help
Choose this option to build a kernel for release 2 or later of the
MIPS32 architecture including features from the 3.5 release such as
@ -1846,7 +1852,7 @@ config CPU_MIPS32_3_5_EVA
config CPU_MIPS32_R5_FEATURES
bool "MIPS32 Release 5 Features"
depends on SYS_HAS_CPU_MIPS32_R5
depends on CPU_MIPS32_R2
depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
help
Choose this option to build a kernel for release 2 or later of the
MIPS32 architecture including features from release 5 such as
@ -2001,6 +2007,10 @@ config SYS_HAS_CPU_MIPS64_R6
bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_P5600
bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_R3000
bool
@ -2084,11 +2094,13 @@ endmenu
#
config CPU_MIPS32
bool
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
CPU_MIPS32_R6 || CPU_P5600
config CPU_MIPS64
bool
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
CPU_MIPS64_R6
#
# These indicate the revision of the architecture
@ -2104,6 +2116,13 @@ config CPU_MIPSR2
select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select MIPS_SPRAM
config CPU_MIPSR5
bool
default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
select CPU_HAS_RIXI
select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select MIPS_SPRAM
config CPU_MIPSR6
bool
default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
@ -2118,6 +2137,7 @@ config TARGET_ISA_REV
int
default 1 if CPU_MIPSR1
default 2 if CPU_MIPSR2
default 5 if CPU_MIPSR5
default 6 if CPU_MIPSR6
default 0
help
@ -2707,7 +2727,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
config RELOCATABLE
bool "Relocatable kernel"
depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
depends on SYS_SUPPORTS_RELOCATABLE
depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
CPU_P5600 || CAVIUM_OCTEON_SOC
help
This builds a kernel image that retains relocation information
so it can be loaded someplace besides the default 1MB.
@ -3275,3 +3299,5 @@ endmenu
source "drivers/firmware/Kconfig"
source "arch/mips/kvm/Kconfig"
source "arch/mips/vdso/Kconfig"

10
arch/mips/Kconfig.debug
View File

@ -148,4 +148,14 @@ config MIPS_CPS_NS16550_SHIFT
form their addresses. That is, log base 2 of the span between
adjacent ns16550 registers in the system.
config MIPS_CPS_NS16550_WIDTH
int "UART Register Width"
default 1
help
ns16550 registers width. UART registers IO access methods will be
selected in accordance with this parameter. By setting it to 1, 2 or
4 UART registers will be accessed by means of lb/sb, lh/sh or lw/sw
instructions respectively. Any value not from that set activates
lb/sb instructions.
endif # MIPS_CPS_NS16550_BOOL

48
arch/mips/Makefile
View File

@ -116,33 +116,8 @@ endif
cflags-y += -ffreestanding
#
# We explicitly add the endianness specifier if needed, this allows
# to compile kernels with a toolchain for the other endianness. We
# carefully avoid to add it redundantly because gcc 3.3/3.4 complains
# when fed the toolchain default!
#
# Certain gcc versions up to gcc 4.1.1 (probably 4.2-subversion as of
# 2006-10-10 don't properly change the predefined symbols if -EB / -EL
# are used, so we kludge that here. A bug has been filed at
# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413.
#
# clang doesn't suffer from these issues and our checks against -dumpmachine
# don't work so well when cross compiling, since without providing --target
# clang's output will be based upon the build machine. So for clang we simply
# unconditionally specify -EB or -EL as appropriate.
#
ifdef CONFIG_CC_IS_CLANG
cflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -EL
else
undef-all += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__
undef-all += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__
predef-be += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__
predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
endif
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
-fno-omit-frame-pointer
@ -171,10 +146,13 @@ cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \
-Wa,--trap
@ -288,12 +266,23 @@ ifdef CONFIG_64BIT
endif
endif
# When linking a 32-bit executable the LLVM linker cannot cope with a
# 32-bit load address that has been sign-extended to 64 bits. Simply
# remove the upper 32 bits then, as it is safe to do so with other
# linkers.
ifdef CONFIG_64BIT
load-ld = $(load-y)
else
load-ld = $(subst 0xffffffff,0x,$(load-y))
endif
KBUILD_AFLAGS += $(cflags-y)
KBUILD_CFLAGS += $(cflags-y)
KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) -DLINKER_LOAD_ADDRESS=$(load-ld)
KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
LINKER_LOAD_ADDRESS=$(load-ld) \
VMLINUX_ENTRY_ADDRESS=$(entry-y) \
PLATFORM="$(platform-y)" \
ITS_INPUTS="$(its-y)"
@ -359,12 +348,6 @@ ifeq ($(shell expr $(zload-y) \< 0xffffffff80000000 2> /dev/null), 0)
bootz-y += uzImage.bin
endif
ifdef CONFIG_LASAT
rom.bin rom.sw: vmlinux
$(Q)$(MAKE) $(build)=arch/mips/lasat/image \
$(bootvars-y) $@
endif
#
# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
@ -430,7 +413,6 @@ archclean:
$(Q)$(MAKE) $(clean)=arch/mips/boot
$(Q)$(MAKE) $(clean)=arch/mips/boot/compressed
$(Q)$(MAKE) $(clean)=arch/mips/boot/tools
$(Q)$(MAKE) $(clean)=arch/mips/lasat
archheaders:
$(Q)$(MAKE) $(build)=arch/mips/kernel/syscalls all

3
arch/mips/alchemy/Platform
View File

@ -15,19 +15,16 @@ load-$(CONFIG_MIPS_DB1XXX) += 0xffffffff80100000
#
# 4G-Systems MTX-1 "MeshCube" wireless router
#
platform-$(CONFIG_MIPS_MTX1) += alchemy/
load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
#
# MyCable eval board
#
platform-$(CONFIG_MIPS_XXS1500) += alchemy/
load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
#
# Trapeze ITS GRP board
#
platform-$(CONFIG_MIPS_GPR) += alchemy/
load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000
# boards can specify their own <gpio.h> in one of their include dirs.

17
arch/mips/alchemy/common/setup.c
View File

@ -27,6 +27,7 @@
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <asm/dma-coherence.h>
#include <asm/mipsregs.h>
@ -72,9 +73,9 @@ void __init plat_mem_setup(void)
iomem_resource.end = IOMEM_RESOURCE_END;
}
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
/* This routine should be valid for all Au1x based boards */
phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
unsigned long start = ALCHEMY_PCI_MEMWIN_START;
unsigned long end = ALCHEMY_PCI_MEMWIN_END;
@ -90,5 +91,13 @@ phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
/* default nop */
return phys_addr;
}
EXPORT_SYMBOL(__fixup_bigphys_addr);
#endif
int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
unsigned long pfn, unsigned long size, pgprot_t prot)
{
phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot);
}
EXPORT_SYMBOL(io_remap_pfn_range);
#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */

2
arch/mips/alchemy/devboards/db1550.c
View File

@ -225,7 +225,7 @@ static void __init pb1550_nand_setup(void)
case 0: case 2: case 8: case 0xC: case 0xD:
/* x16 NAND Flash */
pb1550_nand_pd.devwidth = 1;
/* fallthrough */
fallthrough;
case 1: case 3: case 9: case 0xE: case 0xF:
/* x8 NAND, already set up */
platform_device_register(&pb1550_nand_dev);

1
arch/mips/ar7/Platform
View File

@ -1,6 +1,5 @@
#
# Texas Instruments AR7
#
platform-$(CONFIG_AR7) += ar7/
cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
load-$(CONFIG_AR7) += 0xffffffff94100000

2
arch/mips/ar7/setup.c
View File

@ -57,7 +57,7 @@ const char *get_system_type(void)
case TITAN_CHIP_1060:
return "TI AR7 (TNETV1060)";
}
/* fall through */
fallthrough;
default:
return "TI AR7 (unknown)";
}

1
arch/mips/ath25/Platform
View File

@ -1,6 +1,5 @@
#
# Atheros AR531X/AR231X WiSoC
#
platform-$(CONFIG_ATH25) += ath25/
cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
load-$(CONFIG_ATH25) += 0xffffffff80041000

1
arch/mips/ath79/Platform
View File

@ -2,6 +2,5 @@
# Atheros AR71xx/AR724x/AR913x
#
platform-$(CONFIG_ATH79) += ath79/
cflags-$(CONFIG_ATH79) += -I$(srctree)/arch/mips/include/asm/mach-ath79
load-$(CONFIG_ATH79) = 0xffffffff80060000

3
arch/mips/ath79/setup.c
View File

@ -153,8 +153,7 @@ static void __init ath79_detect_sys_type(void)
case REV_ID_MAJOR_QCA9533_V2:
ver = 2;
ath79_soc_rev = 2;
/* fall through */
fallthrough;
case REV_ID_MAJOR_QCA9533:
ath79_soc = ATH79_SOC_QCA9533;
chip = "9533";

1
arch/mips/bcm47xx/Platform
View File

@ -1,7 +1,6 @@
#
# Broadcom BCM47XX boards
#
platform-$(CONFIG_BCM47XX) += bcm47xx/
cflags-$(CONFIG_BCM47XX) += \
-I$(srctree)/arch/mips/include/asm/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000

1
arch/mips/bcm63xx/Platform
View File

@ -1,7 +1,6 @@
#
# Broadcom BCM63XX boards
#
platform-$(CONFIG_BCM63XX) += bcm63xx/
cflags-$(CONFIG_BCM63XX) += \
-I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
load-$(CONFIG_BCM63XX) := 0xffffffff80010000

2
arch/mips/bcm63xx/cpu.c
View File

@ -304,7 +304,7 @@ void __init bcm63xx_cpu_init(void)
case CPU_BMIPS3300:
if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
__cpu_name[cpu] = "Broadcom BCM6338";
/* fall-through */
fallthrough;
case CPU_BMIPS32:
chipid_reg = BCM_6345_PERF_BASE;
break;

2
arch/mips/bcm63xx/dev-flash.c
View File

@ -94,7 +94,7 @@ static int __init bcm63xx_detect_flash_type(void)
case STRAPBUS_6368_BOOT_SEL_PARALLEL:
return BCM63XX_FLASH_TYPE_PARALLEL;
}
/* fall through */
fallthrough;
default:
return -EINVAL;
}

1
arch/mips/bmips/Platform
View File

@ -1,7 +1,6 @@
#
# Broadcom Generic BMIPS kernel
#
platform-$(CONFIG_BMIPS_GENERIC) += bmips/
cflags-$(CONFIG_BMIPS_GENERIC) += \
-I$(srctree)/arch/mips/include/asm/mach-bmips/
load-$(CONFIG_BMIPS_GENERIC) := 0xffffffff80010000

2
arch/mips/boot/compressed/Makefile
View File

@ -90,7 +90,7 @@ ifneq ($(zload-y),)
VMLINUZ_LOAD_ADDRESS := $(zload-y)
else
VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
$(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
$(obj)/vmlinux.bin $(LINKER_LOAD_ADDRESS))
endif
UIMAGE_LOADADDR = $(VMLINUZ_LOAD_ADDRESS)

30
arch/mips/boot/dts/Makefile
View File

@ -1,17 +1,19 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += brcm
subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
subdir-y += ni
subdir-y += pic32
subdir-y += qca
subdir-y += ralink
subdir-y += xilfpga
subdir-$(CONFIG_BMIPS_GENERIC) += brcm
subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon
subdir-$(CONFIG_MACH_PISTACHIO) += img
subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
subdir-$(CONFIG_MACH_INGENIC) += ingenic
subdir-$(CONFIG_LANTIQ) += lantiq
subdir-$(CONFIG_MACH_LOONGSON64) += loongson
subdir-$(CONFIG_MSCC_OCELOT) += mscc
subdir-$(CONFIG_MIPS_MALTA) += mti
subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
subdir-$(CONFIG_NLM_XLP_BOARD) += netlogic
subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni
subdir-$(CONFIG_MACH_PIC32) += pic32
subdir-$(CONFIG_ATH79) += qca
subdir-$(CONFIG_RALINK) += ralink
subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

3
arch/mips/boot/dts/ingenic/ci20.dts
View File

@ -386,6 +386,9 @@
interrupt-parent = <&gpe>;
interrupts = <19 4>;
nvmem-cells = <&eth0_addr>;
nvmem-cell-names = "mac-address";
};
};

507
arch/mips/boot/dts/ingenic/gcw0.dts
View File

@ -4,6 +4,10 @@
#include "jz4770.dtsi"
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/adc/ingenic,adc.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "gcw,zero", "ingenic,jz4770";
model = "GCW Zero";
@ -15,20 +19,370 @@
serial3 = &uart3;
};
memory: memory {
device_type = "memory";
reg = <0x0 0x10000000>,
<0x30000000 0x10000000>;
};
chosen {
stdout-path = "serial2:57600n8";
};
board {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
vcc: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "vcc";
otg_phy: otg-phy {
compatible = "usb-nop-xceiv";
clocks = <&cgu JZ4770_CLK_OTG_PHY>;
clock-names = "main_clk";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
mmc1_power: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "mmc1_vcc";
gpio = <&gpe 9 0>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc>;
};
headphones_amp: analog-amplifier@0 {
compatible = "simple-audio-amplifier";
enable-gpios = <&gpf 3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <50>;
VCC-supply = <&ldo5>;
sound-name-prefix = "Headphones Amp";
};
speaker_amp: analog-amplifier@1 {
compatible = "simple-audio-amplifier";
enable-gpios = <&gpf 20 GPIO_ACTIVE_HIGH>;
VCC-supply = <&ldo5>;
sound-name-prefix = "Speaker Amp";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "gcw0-audio";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Speaker", "Speaker",
"Headphone", "Headphones",
"Line", "FM Radio",
"Microphone", "Built-in Mic";
simple-audio-card,routing =
"Headphones Amp INL", "LHPOUT",
"Headphones Amp INR", "RHPOUT",
"Headphones", "Headphones Amp OUTL",
"Headphones", "Headphones Amp OUTR",
"Speaker Amp INL", "LOUT",
"Speaker Amp INR", "ROUT",
"Speaker", "Speaker Amp OUTL",
"Speaker", "Speaker Amp OUTR",
"LLINEIN", "FM Radio",
"RLINEIN", "FM Radio",
"Built-in Mic", "MICBIAS",
"MIC1P", "Built-in Mic",
"MIC1N", "Built-in Mic";
simple-audio-card,pin-switches = "Speaker", "Headphones";
simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_HIGH>;
simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>;
simple-audio-card,bitclock-master = <&dai_codec>;
simple-audio-card,frame-master = <&dai_codec>;
dai_cpu: simple-audio-card,cpu {
sound-dai = <&aic>;
};
dai_codec: simple-audio-card,codec {
sound-dai = <&codec>;
};
};
rumble {
compatible = "pwm-vibrator";
pwms = <&pwm 4 2000000 0>;
pwm-names = "enable";
pinctrl-names = "default";
pinctrl-0 = <&pins_pwm4>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 1 40000 0>;
power-supply = <&vcc>;
brightness-levels = <0 16 32 48 64 80 96 112 128
144 160 176 192 208 224 240 255>;
default-brightness-level = <12>;
pinctrl-names = "default";
pinctrl-0 = <&pins_pwm1>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
label = "D-pad up";
linux,code = <KEY_UP>;
linux,can-disable;
gpios = <&gpe 21 GPIO_ACTIVE_LOW>;
};
button@1 {
label = "D-pad down";
linux,code = <KEY_DOWN>;
linux,can-disable;
gpios = <&gpe 25 GPIO_ACTIVE_LOW>;
};
button@2 {
label = "D-pad left";
linux,code = <KEY_LEFT>;
linux,can-disable;
gpios = <&gpe 23 GPIO_ACTIVE_LOW>;
};
button@3 {
label = "D-pad right";
linux,code = <KEY_RIGHT>;
linux,can-disable;
gpios = <&gpe 24 GPIO_ACTIVE_LOW>;
};
button@4 {
label = "Button A";
linux,code = <KEY_LEFTCTRL>;
linux,can-disable;
gpios = <&gpe 29 GPIO_ACTIVE_LOW>;
};
button@5 {
label = "Button B";
linux,code = <KEY_LEFTALT>;
linux,can-disable;
gpios = <&gpe 20 GPIO_ACTIVE_LOW>;
};
button@6 {
label = "Button Y";
linux,code = <KEY_SPACE>;
linux,can-disable;
gpios = <&gpe 27 GPIO_ACTIVE_LOW>;
};
button@7 {
label = "Button X";
linux,code = <KEY_LEFTSHIFT>;
linux,can-disable;
gpios = <&gpe 28 GPIO_ACTIVE_LOW>;
};
button@8 {
label = "Left shoulder button";
linux,code = <KEY_TAB>;
linux,can-disable;
gpios = <&gpb 20 GPIO_ACTIVE_LOW>;
};
button@9 {
label = "Right shoulder button";
linux,code = <KEY_BACKSPACE>;
linux,can-disable;
gpios = <&gpe 26 GPIO_ACTIVE_LOW>;
};
button@10 {
label = "Start button";
linux,code = <KEY_ENTER>;
linux,can-disable;
gpios = <&gpb 21 GPIO_ACTIVE_LOW>;
};
button@11 {
label = "Select button";
linux,code = <KEY_ESC>;
linux,can-disable;
/*
* This is the only button that is active high,
* since it doubles as BOOT_SEL1.
*/
gpios = <&gpd 18 GPIO_ACTIVE_HIGH>;
};
button@12 {
label = "Power slider";
linux,code = <KEY_POWER>;
linux,can-disable;
gpios = <&gpa 30 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button@13 {
label = "Power hold";
linux,code = <KEY_PAUSE>;
linux,can-disable;
gpios = <&gpf 11 GPIO_ACTIVE_LOW>;
};
};
i2c3: i2c-controller@3 {
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
sda-gpios = <&gpd 5 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpd 4 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <2>; /* 250 kHz */
act8600: pmic@5a {
compatible = "active-semi,act8600";
reg = <0x5a>;
regulators {
/* USB OTG */
otg_vbus: SUDCDC_REG4 {
/*
* 5.3V instead of 5.0V to compensate
* for the voltage drop of a diode
* between the regulator and the
* connector.
*/
regulator-min-microvolt = <5300000>;
regulator-max-microvolt = <5300000>;
inl-supply = <&vcc>;
};
/*
* When this is off, there is no sound, but also
* no USB networking.
*/
ldo5: LDO5 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
inl-supply = <&vcc>;
};
/* LCD panel and FM radio */
ldo6: LDO6 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
inl-supply = <&vcc>;
};
/* ??? */
LDO7 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/*regulator-always-on;*/
inl-supply = <&vcc>;
};
/*
* The colors on the LCD are wrong when this is
* off. Which is strange, since the LCD panel
* data sheet only mentions a 3.3V input.
*/
LDO8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
inl-supply = <&vcc>;
};
/* RTC fixed 3.3V */
LDO_REG9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
inl-supply = <&vcc>;
};
/* Unused fixed 1.2V */
LDO_REG10 {
inl-supply = <&vcc>;
};
};
};
};
leds {
compatible = "gpio-leds";
led {
gpios = <&gpb 30 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpe 15 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpe 17 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpe 16 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
nt39016@0 {
compatible = "kingdisplay,kd035g6-54nt";
reg = <0>;
spi-max-frequency = <3125000>;
spi-3wire;
spi-cs-high;
reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
backlight = <&backlight>;
power-supply = <&ldo6>;
port {
panel_input: endpoint {
remote-endpoint = <&panel_output>;
};
};
};
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
label = "mini-USB";
type = "mini";
/*
* USB OTG is not yet working reliably, the ID detection
* mechanism tends to fry easily for unknown reasons.
* Until this is fixed, disable OTG by not providing the
* ID GPIO to the driver.
*/
//id-gpios = <&gpf 18 GPIO_ACTIVE_LOW>;
vbus-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
vbus-supply = <&otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pins_otg>;
port {
usb_ep: endpoint {
remote-endpoint = <&usb_otg_ep>;
};
};
};
};
@ -37,24 +391,86 @@
clock-frequency = <12000000>;
};
&pinctrl {
pins_lcd: lcd {
function = "lcd";
groups = "lcd-24bit";
};
pins_uart2: uart2 {
function = "uart2";
groups = "uart2-data";
};
pins_mmc0: mmc0 {
function = "mmc0";
groups = "mmc0-1bit-a", "mmc0-4bit-a";
};
pins_mmc1: mmc1 {
function = "mmc1";
groups = "mmc1-1bit-d", "mmc1-4bit-d";
};
pins_otg: otg {
otg-vbus-pin {
function = "otg";
groups = "otg-vbus";
};
vbus-pin {
pins = "PB5";
bias-disable;
};
};
pins_pwm1: pwm1 {
function = "pwm1";
groups = "pwm1";
};
pins_pwm4: pwm4 {
function = "pwm4";
groups = "pwm4";
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pins_uart2>;
status = "okay";
};
&cgu {
/* Put high-speed peripherals under PLL1, such that we can change the
/*
* Put high-speed peripherals under PLL1, such that we can change the
* PLL0 frequency on demand without having to suspend peripherals.
* We use a rate of 432 MHz, which is the least common multiple of
* 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
* Put the GPU under PLL0 since we want a higher frequency.
* Use the 32 kHz oscillator as the parent of the RTC for a higher
* precision.
*/
assigned-clocks =
<&cgu JZ4770_CLK_PLL1>,
<&cgu JZ4770_CLK_UHC>;
<&cgu JZ4770_CLK_GPU>,
<&cgu JZ4770_CLK_RTC>,
<&cgu JZ4770_CLK_UHC>,
<&cgu JZ4770_CLK_LPCLK_MUX>,
<&cgu JZ4770_CLK_MMC0_MUX>,
<&cgu JZ4770_CLK_MMC1_MUX>;
assigned-clock-parents =
<0>,
<&cgu JZ4770_CLK_PLL0>,
<&cgu JZ4770_CLK_OSC32K>,
<&cgu JZ4770_CLK_PLL1>,
<&cgu JZ4770_CLK_PLL1>,
<&cgu JZ4770_CLK_PLL1>,
<&cgu JZ4770_CLK_PLL1>;
assigned-clock-rates =
<432000000>;
<432000000>,
<600000000>;
};
&uhc {
@ -63,10 +479,69 @@
};
&tcu {
/* 750 kHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
assigned-clock-rates = <750000>, <750000>;
/*
* 750 kHz for the system timer and clocksource, 12 MHz for the OST,
* and use RTC as the parent for the watchdog clock
*/
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>,
<&tcu TCU_CLK_OST>, <&tcu TCU_CLK_WDT>;
assigned-clock-parents = <0>, <0>, <0>, <&cgu JZ4770_CLK_RTC>;
assigned-clock-rates = <750000>, <750000>, <12000000>;
/* PWM1 is in use, so reserve channel #2 for the clocksource */
/* PWM1 is in use, so use channel #2 for the clocksource */
ingenic,pwm-channels-mask = <0xfa>;
};
&usb_otg {
port {
usb_otg_ep: endpoint {
remote-endpoint = <&usb_ep>;
};
};
};
&otg_phy {
vcc-supply = <&ldo5>;
};
&rtc {
clocks = <&cgu JZ4770_CLK_RTC>;
clock-names = "rtc";
system-power-controller;
};
&mmc0 {
status = "okay";
bus-width = <4>;
max-frequency = <48000000>;
vmmc-supply = <&vcc>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&pins_mmc0>;
};
&mmc1 {
status = "okay";
bus-width = <4>;
max-frequency = <48000000>;
cd-gpios = <&gpb 2 GPIO_ACTIVE_LOW>;
vmmc-supply = <&mmc1_power>;
pinctrl-names = "default";
pinctrl-0 = <&pins_mmc1>;
};
&lcd {
pinctrl-names = "default";
pinctrl-0 = <&pins_lcd>;
port {
panel_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};

13
arch/mips/boot/dts/ingenic/gcw0_proto.dts Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "gcw0.dts"
/ {
model = "GCW Zero Prototype";
};
&memory {
/* Prototype has only 256 MiB of RAM */
reg = <0x0 0x10000000>;
};

33
arch/mips/boot/dts/ingenic/jz4740.dtsi
View File

@ -55,10 +55,10 @@
#clock-cells = <1>;
clocks = <&cgu JZ4740_CLK_RTC
&cgu JZ4740_CLK_EXT
&cgu JZ4740_CLK_PCLK
&cgu JZ4740_CLK_TCU>;
clocks = <&cgu JZ4740_CLK_RTC>,
<&cgu JZ4740_CLK_EXT>,
<&cgu JZ4740_CLK_PCLK>,
<&cgu JZ4740_CLK_TCU>;
clock-names = "rtc", "ext", "pclk", "tcu";
interrupt-controller;
@ -74,6 +74,20 @@
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
pwm: pwm@40 {
compatible = "ingenic,jz4740-pwm";
reg = <0x40 0x80>;
#pwm-cells = <3>;
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
<&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
clock-names = "timer0", "timer1", "timer2", "timer3",
"timer4", "timer5", "timer6", "timer7";
};
};
rtc_dev: rtc@10003000 {
@ -241,10 +255,10 @@
reg = <0x13010000 0x54>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x18000000 0x4000000
2 0 0x14000000 0x4000000
3 0 0x0c000000 0x4000000
4 0 0x08000000 0x4000000>;
ranges = <1 0 0x18000000 0x4000000>,
<2 0 0x14000000 0x4000000>,
<3 0 0x0c000000 0x4000000>,
<4 0 0x08000000 0x4000000>;
clocks = <&cgu JZ4740_CLK_MCLK>;
};
@ -258,8 +272,7 @@
dmac: dma-controller@13020000 {
compatible = "ingenic,jz4740-dma";
reg = <0x13020000 0xbc
0x13020300 0x14>;
reg = <0x13020000 0xbc>, <0x13020300 0x14>;
#dma-cells = <2>;
interrupt-parent = <&intc>;

227
arch/mips/boot/dts/ingenic/jz4770.dtsi
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/jz4770-cgu.h>
#include <dt-bindings/clock/ingenic,tcu.h>
/ {
#address-cells = <1>;
@ -37,13 +38,25 @@
};
cgu: jz4770-cgu@10000000 {
compatible = "ingenic,jz4770-cgu";
compatible = "ingenic,jz4770-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0x100>;
clocks = <&ext>, <&osc32k>;
clock-names = "ext", "osc32k";
#clock-cells = <1>;
otg_phy: usb-phy@3c {
compatible = "ingenic,jz4770-phy";
reg = <0x3c 0x10>;
clocks = <&cgu JZ4770_CLK_OTG_PHY>;
#phy-cells = <0>;
};
};
tcu: timer@10002000 {
@ -55,9 +68,9 @@
#clock-cells = <1>;
clocks = <&cgu JZ4770_CLK_RTC
&cgu JZ4770_CLK_EXT
&cgu JZ4770_CLK_PCLK>;
clocks = <&cgu JZ4770_CLK_RTC>,
<&cgu JZ4770_CLK_EXT>,
<&cgu JZ4770_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
@ -65,6 +78,47 @@
interrupt-parent = <&intc>;
interrupts = <27 26 25>;
watchdog: watchdog@0 {
compatible = "ingenic,jz4770-watchdog",
"ingenic,jz4740-watchdog";
reg = <0x0 0xc>;
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
pwm: pwm@40 {
compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm";
reg = <0x40 0x80>;
#pwm-cells = <3>;
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
<&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
clock-names = "timer0", "timer1", "timer2", "timer3",
"timer4", "timer5", "timer6", "timer7";
};
ost: timer@e0 {
compatible = "ingenic,jz4770-ost";
reg = <0xe0 0x20>;
clocks = <&tcu TCU_CLK_OST>;
clock-names = "ost";
interrupts = <15>;
};
};
rtc: rtc@10003000 {
compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc";
reg = <0x10003000 0x40>;
interrupt-parent = <&intc>;
interrupts = <32>;
};
pinctrl: pin-controller@10010000 {
@ -165,6 +219,93 @@
};
};
aic: audio-controller@10020000 {
compatible = "ingenic,jz4770-i2s";
reg = <0x10020000 0x94>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
<&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
clock-names = "aic", "i2s", "ext", "pll half";
interrupt-parent = <&intc>;
interrupts = <34>;
dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>;
dma-names = "rx", "tx";
};
codec: audio-codec@100200a0 {
compatible = "ingenic,jz4770-codec";
reg = <0x100200a4 0x8>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4770_CLK_AIC>;
clock-names = "aic";
};
mmc0: mmc@10021000 {
compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
reg = <0x10021000 0x1000>;
clocks = <&cgu JZ4770_CLK_MMC0>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <37>;
dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
status = "disabled";
};
mmc1: mmc@10022000 {
compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
reg = <0x10022000 0x1000>;
clocks = <&cgu JZ4770_CLK_MMC1>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <36>;
dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
status = "disabled";
};
mmc2: mmc@10023000 {
compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
reg = <0x10023000 0x1000>;
clocks = <&cgu JZ4770_CLK_MMC2>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <35>;
dmas = <&dmac1 37 0xffffffff>, <&dmac1 36 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
status = "disabled";
};
uart0: serial@10030000 {
compatible = "ingenic,jz4770-uart";
reg = <0x10030000 0x100>;
@ -217,34 +358,63 @@
status = "disabled";
};
adc: adc@10070000 {
compatible = "ingenic,jz4770-adc";
reg = <0x10070000 0x30>;
#io-channel-cells = <1>;
clocks = <&cgu JZ4770_CLK_ADC>;
clock-names = "adc";
interrupt-parent = <&intc>;
interrupts = <18>;
};
gpu: gpu@13040000 {
compatible = "vivante,gc";
reg = <0x13040000 0x10000>;
clocks = <&cgu JZ4770_CLK_GPU>,
<&cgu JZ4770_CLK_GPU>,
<&cgu JZ4770_CLK_GPU>;
clock-names = "bus", "core", "shader";
interrupt-parent = <&intc>;
interrupts = <6>;
};
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4770-lcd";
reg = <0x13050000 0x300>;
interrupt-parent = <&intc>;
interrupts = <31>;
clocks = <&cgu JZ4770_CLK_LPCLK_MUX>;
clock-names = "lcd_pclk";
};
dmac0: dma-controller@13420000 {
compatible = "ingenic,jz4770-dma";
reg = <0x13420000 0xC0
0x13420300 0x20>;
reg = <0x13420000 0xC0>, <0x13420300 0x20>;
#dma-cells = <1>;
#dma-cells = <2>;
clocks = <&cgu JZ4770_CLK_DMA>;
interrupt-parent = <&intc>;
interrupts = <24>;
/* Disable dmac0 until we have something that uses it */
status = "disabled";
};
dmac1: dma-controller@13420100 {
compatible = "ingenic,jz4770-dma";
reg = <0x13420100 0xC0
0x13420400 0x20>;
reg = <0x13420100 0xC0>, <0x13420400 0x20>;
#dma-cells = <1>;
#dma-cells = <2>;
clocks = <&cgu JZ4770_CLK_DMA>;
interrupt-parent = <&intc>;
interrupts = <23>;
/* Disable dmac1 until we have something that uses it */
status = "disabled";
};
uhc: uhc@13430000 {
@ -260,4 +430,29 @@
status = "disabled";
};
usb_otg: usb@13440000 {
compatible = "ingenic,jz4770-musb";
reg = <0x13440000 0x10000>;
clocks = <&cgu JZ4770_CLK_OTG>;
clock-names = "udc";
interrupt-parent = <&intc>;
interrupts = <21>;
interrupt-names = "mc";
phys = <&otg_phy>;
usb-role-switch;
};
rom: memory@1fc00000 {
compatible = "mtd-rom";
probe-type = "map_rom";
reg = <0x1fc00000 0x2000>;
bank-width = <4>;
device-width = <1>;
};
};

65
arch/mips/boot/dts/ingenic/jz4780.dtsi
View File

@ -58,9 +58,9 @@
#clock-cells = <1>;
clocks = <&cgu JZ4780_CLK_RTCLK
&cgu JZ4780_CLK_EXCLK
&cgu JZ4780_CLK_PCLK>;
clocks = <&cgu JZ4780_CLK_RTCLK>,
<&cgu JZ4780_CLK_EXCLK>,
<&cgu JZ4780_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
@ -76,6 +76,30 @@
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
pwm: pwm@40 {
compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm";
reg = <0x40 0x80>;
#pwm-cells = <3>;
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
<&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
clock-names = "timer0", "timer1", "timer2", "timer3",
"timer4", "timer5", "timer6", "timer7";
};
ost: timer@e0 {
compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost";
reg = <0xe0 0x20>;
clocks = <&tcu TCU_CLK_OST>;
clock-names = "ost";
interrupts = <15>;
};
};
rtc_dev: rtc@10003000 {
@ -196,8 +220,7 @@
gpio-miso = <&gpe 14 0>;
gpio-sck = <&gpe 15 0>;
gpio-mosi = <&gpe 17 0>;
cs-gpios = <&gpe 16 0
&gpe 18 0>;
cs-gpios = <&gpe 16 0>, <&gpe 18 0>;
spidev@0 {
compatible = "spidev";
@ -358,26 +381,40 @@
};
nemc: nemc@13410000 {
compatible = "ingenic,jz4780-nemc";
compatible = "ingenic,jz4780-nemc", "simple-mfd";
reg = <0x13410000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x1b000000 0x1000000
2 0 0x1a000000 0x1000000
3 0 0x19000000 0x1000000
4 0 0x18000000 0x1000000
5 0 0x17000000 0x1000000
6 0 0x16000000 0x1000000>;
ranges = <0 0 0x13410000 0x10000>,
<1 0 0x1b000000 0x1000000>,
<2 0 0x1a000000 0x1000000>,
<3 0 0x19000000 0x1000000>,
<4 0 0x18000000 0x1000000>,
<5 0 0x17000000 0x1000000>,
<6 0 0x16000000 0x1000000>;
clocks = <&cgu JZ4780_CLK_NEMC>;
status = "disabled";
efuse: efuse@d0 {
reg = <0 0xd0 0x30>;
compatible = "ingenic,jz4780-efuse";
clocks = <&cgu JZ4780_CLK_AHB2>;
#address-cells = <1>;
#size-cells = <1>;
eth0_addr: eth-mac-addr@0x22 {
reg = <0x22 0x6>;
};
};
};
dma: dma@13420000 {
compatible = "ingenic,jz4780-dma";
reg = <0x13420000 0x400
0x13421000 0x40>;
reg = <0x13420000 0x400>, <0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;

9
arch/mips/boot/dts/ingenic/x1000.dtsi
View File

@ -58,9 +58,9 @@
#clock-cells = <1>;
clocks = <&cgu X1000_CLK_RTCLK
&cgu X1000_CLK_EXCLK
&cgu X1000_CLK_PCLK>;
clocks = <&cgu X1000_CLK_RTCLK>,
<&cgu X1000_CLK_EXCLK>,
<&cgu X1000_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
@ -239,8 +239,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1000-dma";
reg = <0x13420000 0x400
0x13421000 0x40>;
reg = <0x13420000 0x400>, <0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;

17
arch/mips/boot/dts/loongson/rs780e-pch.dtsi
View File

@ -9,6 +9,18 @@
0 0x40000000 0 0x40000000 0 0x40000000
0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
pci@1a000000 {
compatible = "loongson,rs780e-pci";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x1a000000 0 0x02000000>;
ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
<0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
};
isa {
compatible = "isa";
#address-cells = <2>;
@ -21,6 +33,11 @@
interrupts = <8>;
interrupt-parent = <&htpic>;
};
acpi@800 {
compatible = "loongson,rs780e-acpi";
reg = <1 0x800 0x100>;
};
};
};
};

2
arch/mips/boot/dts/mscc/ocelot.dtsi
View File

@ -214,7 +214,7 @@
miim1: miim1 {
pins = "GPIO_14", "GPIO_15";
function = "miim1";
function = "miim";
};
};

2
arch/mips/boot/dts/qca/ar9331.dtsi
View File

@ -59,7 +59,7 @@
#qca,ddr-wb-channel-cells = <1>;
};
uart: uart@18020000 {
uart: serial@18020000 {
compatible = "qca,ar9330-uart";
reg = <0x18020000 0x14>;

6
arch/mips/boot/dts/qca/ar9331_dpt_module.dts
View File

@ -3,6 +3,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "ar9331.dtsi"
@ -22,8 +23,9 @@
leds {
compatible = "gpio-leds";
system {
label = "dpt-module:green:system";
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
default-state = "off";
};

1
arch/mips/cavium-octeon/Platform
View File

@ -1,7 +1,6 @@
#
# Cavium Octeon
#
platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \
-I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000

12
arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
View File

@ -59,18 +59,6 @@ int __cvmx_helper_npi_probe(int interface)
&& !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
/* The packet engines didn't exist before pass 2 */
return 4;
#if 0
/*
* Technically CN30XX, CN31XX, and CN50XX contain packet
* engines, but nobody ever uses them. Since this is the case,
* we disable them here.
*/
else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX))
return 2;
else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
return 1;
#endif
#endif
return 0;
}

2
arch/mips/cavium-octeon/executive/cvmx-pko.c
View File

@ -489,7 +489,7 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
config.s.qos_mask = 0xff;
break;
}
/* fall through - to the error case, when Pass 1 */
fallthrough; /* to the error case, when Pass 1 */
default:
cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
"priority %llu\n",

4
arch/mips/cavium-octeon/octeon-platform.c
View File

@ -141,7 +141,7 @@ static void octeon2_usb_clocks_start(struct device *dev)
default:
pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
clock_rate);
/* Fall through */
fallthrough;
case 12000000:
clk_rst_ctl.s.p_refclk_div = 0;
break;
@ -1116,7 +1116,7 @@ end_led:
new_f[0] = cpu_to_be32(48000000);
fdt_setprop_inplace(initial_boot_params, usbn,
"refclk-frequency", new_f, sizeof(new_f));
/* Fall through ...*/
fallthrough;
case USB_CLOCK_TYPE_REF_12:
/* Missing "refclk-type" defaults to external. */
fdt_nop_property(initial_boot_params, usbn, "refclk-type");

2
arch/mips/cavium-octeon/octeon-usb.c
View File

@ -398,7 +398,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
default:
dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
clock_rate);
/* fall through */
fallthrough;
case 100000000:
mpll_mul = 0x19;
if (ref_clk_sel < 2)

1
arch/mips/cobalt/Platform
View File

@ -1,6 +1,5 @@
#
# Cobalt Server
#
platform-$(CONFIG_MIPS_COBALT) += cobalt/
cflags-$(CONFIG_MIPS_COBALT) += -I$(srctree)/arch/mips/include/asm/mach-cobalt
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000

1
arch/mips/configs/ath79_defconfig
View File

@ -46,7 +46,6 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_NETDEVICES=y
CONFIG_ATH9K=m

62
arch/mips/configs/ci20_defconfig
View File

@ -1,5 +1,4 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_MODULES=y
CONFIG_KERNEL_XZ=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
@ -29,6 +28,7 @@ CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
CONFIG_MODULES=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
@ -38,17 +38,12 @@ CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_JZ4780=y
@ -72,9 +67,8 @@ CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_KEYBOARD_GPIO=m
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=2
CONFIG_SERIAL_8250=y
@ -89,7 +83,7 @@ CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_KEYBOARD_GPIO=m
CONFIG_POWER_SUPPLY=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_JZ4740_WDT=y
@ -97,17 +91,45 @@ CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ACT8865=y
CONFIG_RC_CORE=m
CONFIG_LIRC=y
CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_MEDIA_SUPPORT=m
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_JZ4740=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=m
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
CONFIG_INGENIC_OST=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
CONFIG_PWM=y
CONFIG_PWM_JZ4740=m
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_PROC_KCORE=y
@ -156,11 +178,13 @@ CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_UTF8=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
@ -169,21 +193,3 @@ CONFIG_STACKTRACE=y
# CONFIG_FTRACE is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="earlycon console=ttyS4,115200 clk_ignore_unused"
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=m
CONFIG_LIRC=y
CONFIG_MEDIA_SUPPORT=m
CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m

1
arch/mips/configs/db1xxx_defconfig
View File

@ -92,7 +92,6 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ECC_SW_BCH=y

131
arch/mips/configs/gcw0_defconfig
View File

@ -1,27 +1,152 @@
CONFIG_DEFAULT_HOSTNAME="gcw0"
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
CONFIG_MACH_INGENIC=y
CONFIG_JZ4770_GCW0=y
CONFIG_HIGHMEM=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_MIPS_CMDLINE_DTB_EXTEND=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BOUNCE is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_CFG80211=y
CONFIG_MAC80211=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
CONFIG_NETDEVICES=y
# CONFIG_ETHERNET is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
CONFIG_RTL8192CU=m
# CONFIG_RTLWIFI_DEBUG is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_PWM_VIBRA=y
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_INGENIC=y
CONFIG_HW_RANDOM=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_POWER_SUPPLY=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_JZ4740_WDT=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ACT8865=y
CONFIG_DRM=y
CONFIG_DRM_FBDEV_OVERALLOC=300
CONFIG_DRM_PANEL_NOVATEK_NT39016=y
CONFIG_DRM_INGENIC=y
CONFIG_DRM_ETNAVIV=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_PROC_FS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_MIPS is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_JZ4740_SOC_I2S=y
CONFIG_SND_SOC_JZ4770_CODEC=y
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_USB_CONN_GPIO=y
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_TMPFS=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_JZ4740=y
CONFIG_USB_INVENTRA_DMA=y
CONFIG_JZ4770_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_ETH=y
CONFIG_MMC=y
# CONFIG_PWRSEQ_EMMC is not set
# CONFIG_PWRSEQ_SIMPLE is not set
CONFIG_MMC_JZ4740=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
# CONFIG_VIRTIO_MENU is not set
CONFIG_STAGING=y
CONFIG_R8188EU=m
CONFIG_INGENIC_OST=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_MXC6255=m
CONFIG_INGENIC_ADC=y
CONFIG_PWM=y
CONFIG_PWM_JZ4740=y
CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_DECOMP_MULTI=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity"
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_FONTS=y
CONFIG_FONT_6x10=y
CONFIG_DEBUG_FS=y

1
arch/mips/configs/generic/board-ocelot.config
View File

@ -9,7 +9,6 @@ CONFIG_GENERIC_PHY=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_SPI_NOR=y

55
arch/mips/configs/lasat_defconfig
View File

@ -1,55 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_KALLSYMS is not set
CONFIG_SLAB=y
CONFIG_LASAT=y
CONFIG_PICVUE=y
CONFIG_PICVUE_PROC=y
CONFIG_DS1603=y
CONFIG_LASAT_SYSCTL=y
CONFIG_HZ_1000=y
# CONFIG_SECCOMP is not set
CONFIG_PCI=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_PATA_CMD64X=y
CONFIG_ATA_GENERIC=y
CONFIG_PATA_LEGACY=y
CONFIG_NETDEVICES=y
CONFIG_PCNET32=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_RAW=y
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_MAGIC_SYSRQ=y

4
arch/mips/configs/loongson3_defconfig
View File

@ -21,6 +21,7 @@ CONFIG_SYSFS_DEPRECATED=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_MACH_LOONGSON64=y
CONFIG_SMP=y
CONFIG_HZ_256=y
@ -216,6 +217,7 @@ CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_HW_RANDOM=y
CONFIG_RAW_DRIVER=m
CONFIG_I2C_CHARDEV=y
@ -229,7 +231,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_DRM=y
CONFIG_DRM_RADEON=y
CONFIG_DRM_RADEON=m
CONFIG_FB_RADEON=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=m

185
arch/mips/configs/markeins_defconfig
View File

@ -1,185 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_NEC_MARKEINS=y
CONFIG_HZ_1000=y
CONFIG_PCI=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6_MIP6=m
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_SCSI=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_SG=m
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_AIC94XX=m
# CONFIG_AIC94XX_DEBUG is not set
CONFIG_NETDEVICES=y
CONFIG_TUN=m
CONFIG_CHELSIO_T3=m
CONFIG_NATSEMI=y
CONFIG_QLA3XXX=m
CONFIG_NETXEN_NIC=m
CONFIG_PPP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DEBUG_CORE=y
CONFIG_I2C_DEBUG_BUS=y
# CONFIG_HID is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=m
CONFIG_XFS_FS=m
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS4_FS=m
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=m
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=m
CONFIG_NFSD_V3=y
CONFIG_NLS_DEFAULT=""
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_UTF8=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"

77
arch/mips/configs/msp71xx_defconfig
View File

@ -1,77 +0,0 @@
CONFIG_LOCALVERSION="-pmc"
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_SHMEM is not set
CONFIG_SLAB=y
CONFIG_PMC_MSP=y
CONFIG_PMC_MSP7120_GW=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_NR_CPUS=2
CONFIG_PCI=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_BRIDGE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_RAM=y
CONFIG_MTD_PMC_MSP_EVM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_PPP=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PMCMSP=y
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_STORAGE=y
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_JFFS2_FS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y

1
arch/mips/configs/pistachio_defconfig
View File

@ -127,7 +127,6 @@ CONFIG_DEBUG_DEVRES=y
CONFIG_CONNECTOR=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y

1
arch/mips/configs/rt305x_defconfig
View File

@ -76,7 +76,6 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_EEPROM_93CX6=m
CONFIG_SCSI=y

1
arch/mips/dec/Platform
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@ -1,7 +1,6 @@
#
# DECstation family
#
platform-$(CONFIG_MACH_DECSTATION) += dec/
cflags-$(CONFIG_MACH_DECSTATION) += \
-I$(srctree)/arch/mips/include/asm/mach-dec
libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/

4
arch/mips/dec/int-handler.S
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@ -304,8 +304,8 @@ spurious:
*/
FEXPORT(dec_intr_unimplemented)
move a1,t0 # cheats way of printing an arg!
PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x");
ASM_PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x");
FEXPORT(asic_intr_unimplemented)
move a1,t0 # cheats way of printing an arg!
PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x");
ASM_PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x");

2
arch/mips/dec/tc.c
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@ -52,7 +52,7 @@ int __init tc_bus_get_info(struct tc_bus *tbus)
case MACH_DS5900:
tbus->ext_slot_base = 0x20000000;
tbus->ext_slot_size = 0x20000000;
/* fall through */
fallthrough;
case MACH_DS5000_1XX:
tbus->num_tcslots = 3;
break;

7
arch/mips/emma/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SOC_EMMA2RH) += common/
#
# NEC EMMA2RH Mark-eins
#
obj-$(CONFIG_NEC_MARKEINS) += markeins/

4
arch/mips/emma/Platform
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@ -1,4 +0,0 @@
platform-$(CONFIG_SOC_EMMA2RH) += emma/
cflags-$(CONFIG_SOC_EMMA2RH) += \
-I$(srctree)/arch/mips/include/asm/mach-emma2rh
load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000

6
arch/mips/emma/common/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) NEC Electronics Corporation 2005-2006
#
obj-$(CONFIG_NEC_MARKEINS) += prom.o

56
arch/mips/emma/common/prom.c
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@ -1,56 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/common/prom.c
*
* Copyright 2001 MontaVista Software Inc.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/memblock.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/emma/emma2rh.h>
const char *get_system_type(void)
{
#ifdef CONFIG_NEC_MARKEINS
return "NEC EMMA2RH Mark-eins";
#else
#error Unknown NEC board
#endif
}
/* [jsun@junsun.net] PMON passes arguments in C main() style */
void __init prom_init(void)
{
int argc = fw_arg0;
char **arg = (char **)fw_arg1;
int i;
/* if user passes kernel args, ignore the default one */
if (argc > 1)
arcs_cmdline[0] = '\0';
/* arg[0] is "g", the rest is boot parameters */
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i]) + 1
>= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
#ifdef CONFIG_NEC_MARKEINS
add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
#else
#error Unknown NEC board
#endif
}
void __init prom_free_prom_memory(void)
{
}

6
arch/mips/emma/markeins/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) NEC Electronics Corporation 2005-2006
#
obj-$(CONFIG_NEC_MARKEINS) += irq.o setup.o led.o platform.o

293
arch/mips/emma/markeins/irq.c
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@ -1,293 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
*
* Copyright 2001 MontaVista Software Inc.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/delay.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/emma/emma2rh.h>
static void emma2rh_irq_enable(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_IRQ_BASE;
u32 reg_value, reg_bitmask, reg_index;
reg_index = EMMA2RH_BHIF_INT_EN_0 +
(EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
reg_value = emma2rh_in32(reg_index);
reg_bitmask = 0x1 << (irq % 32);
emma2rh_out32(reg_index, reg_value | reg_bitmask);
}
static void emma2rh_irq_disable(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_IRQ_BASE;
u32 reg_value, reg_bitmask, reg_index;
reg_index = EMMA2RH_BHIF_INT_EN_0 +
(EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
reg_value = emma2rh_in32(reg_index);
reg_bitmask = 0x1 << (irq % 32);
emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
}
struct irq_chip emma2rh_irq_controller = {
.name = "emma2rh_irq",
.irq_mask = emma2rh_irq_disable,
.irq_unmask = emma2rh_irq_enable,
};
void emma2rh_irq_init(void)
{
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq, "level");
}
static void emma2rh_sw_irq_enable(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE;
u32 reg;
reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
}
static void emma2rh_sw_irq_disable(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE;
u32 reg;
reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
}
struct irq_chip emma2rh_sw_irq_controller = {
.name = "emma2rh_sw_irq",
.irq_mask = emma2rh_sw_irq_disable,
.irq_unmask = emma2rh_sw_irq_enable,
};
void emma2rh_sw_irq_init(void)
{
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq, "level");
}
static void emma2rh_gpio_irq_enable(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
u32 reg;
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
static void emma2rh_gpio_irq_disable(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
u32 reg;
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
static void emma2rh_gpio_irq_ack(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
}
static void emma2rh_gpio_irq_mask_ack(struct irq_data *d)
{
unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
u32 reg;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
struct irq_chip emma2rh_gpio_irq_controller = {
.name = "emma2rh_gpio_irq",
.irq_ack = emma2rh_gpio_irq_ack,
.irq_mask = emma2rh_gpio_irq_disable,
.irq_mask_ack = emma2rh_gpio_irq_mask_ack,
.irq_unmask = emma2rh_gpio_irq_enable,
};
void emma2rh_gpio_irq_init(void)
{
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller,
handle_edge_irq, "edge");
}
/*
* the first level int-handler will jump here if it is a emma2rh irq
*/
void emma2rh_irq_dispatch(void)
{
u32 intStatus;
u32 bitmask;
u32 i;
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
#ifdef EMMA2RH_SW_CASCADE
if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) {
u32 swIntStatus;
swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (swIntStatus & bitmask) {
do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
return;
}
}
}
/* Skip S/W interrupt */
intStatus &= ~(1UL << EMMA2RH_SW_CASCADE);
#endif
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
#ifdef EMMA2RH_GPIO_CASCADE
if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) {
u32 gpioIntStatus;
gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (gpioIntStatus & bitmask) {
do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
return;
}
}
}
/* Skip GPIO interrupt */
intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32));
#endif
for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
}
void __init arch_init_irq(void)
{
u32 reg;
int irq;
/* by default, interrupts are disabled. */
emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
clear_c0_status(0xff00);
set_c0_status(0x0400);
#define GPIO_PCI (0xf<<15)
/* setup GPIO interrupt for PCI interface */
/* direction input */
reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
/* disable interrupt */
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
/* level triggerd */
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
/* interrupt clear */
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
/* init all controllers */
emma2rh_irq_init();
emma2rh_sw_irq_init();
emma2rh_gpio_irq_init();
mips_cpu_irq_init();
/* setup cascade interrupts */
irq = EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE;
if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", irq);
irq = EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE;
if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", irq);
irq = MIPS_CPU_IRQ_BASE + 2;
if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", irq);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7)
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else if (pending & STATUSF_IP2)
emma2rh_irq_dispatch();
else if (pending & STATUSF_IP1)
do_IRQ(MIPS_CPU_IRQ_BASE + 1);
else if (pending & STATUSF_IP0)
do_IRQ(MIPS_CPU_IRQ_BASE + 0);
else
spurious_interrupt();
}

44
arch/mips/emma/markeins/led.c
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@ -1,44 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) NEC Electronics Corporation 2004-2006
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/emma/emma2rh.h>
const unsigned long clear = 0x20202020;
#define LED_BASE 0xb1400038
void markeins_led_clear(void)
{
emma2rh_out32(LED_BASE, clear);
emma2rh_out32(LED_BASE + 4, clear);
}
void markeins_led(const char *str)
{
int i;
int len = strlen(str);
markeins_led_clear();
if (len > 8)
len = 8;
if (emma2rh_in32(0xb0000800) & (0x1 << 18))
for (i = 0; i < len; i++)
emma2rh_out8(LED_BASE + i, str[i]);
else
for (i = 0; i < len; i++)
emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)),
str[i]);
}
void markeins_led_hex(u32 val)
{
char str[10];
sprintf(str, "%08x", val);
markeins_led(str);
}

199
arch/mips/emma/markeins/platform.c
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@ -1,199 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright(C) MontaVista Software Inc, 2006
*
* Author: dmitry pervushin <dpervushin@ru.mvista.com>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/time.h>
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/traps.h>
#include <asm/emma/emma2rh.h>
#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
static struct resource i2c_emma_resources_0[] = {
{
.name = NULL,
.start = EMMA2RH_IRQ_PIIC0,
.end = EMMA2RH_IRQ_PIIC0,
.flags = IORESOURCE_IRQ
}, {
.name = NULL,
.start = EMMA2RH_PIIC0_BASE,
.end = EMMA2RH_PIIC0_BASE + 0x1000,
.flags = 0
},
};
struct resource i2c_emma_resources_1[] = {
{
.name = NULL,
.start = EMMA2RH_IRQ_PIIC1,
.end = EMMA2RH_IRQ_PIIC1,
.flags = IORESOURCE_IRQ
}, {
.name = NULL,
.start = EMMA2RH_PIIC1_BASE,
.end = EMMA2RH_PIIC1_BASE + 0x1000,
.flags = 0
},
};
struct resource i2c_emma_resources_2[] = {
{
.name = NULL,
.start = EMMA2RH_IRQ_PIIC2,
.end = EMMA2RH_IRQ_PIIC2,
.flags = IORESOURCE_IRQ
}, {
.name = NULL,
.start = EMMA2RH_PIIC2_BASE,
.end = EMMA2RH_PIIC2_BASE + 0x1000,
.flags = 0
},
};
struct platform_device i2c_emma_devices[] = {
[0] = {
.name = I2C_EMMA2RH,
.id = 0,
.resource = i2c_emma_resources_0,
.num_resources = ARRAY_SIZE(i2c_emma_resources_0),
},
[1] = {
.name = I2C_EMMA2RH,
.id = 1,
.resource = i2c_emma_resources_1,
.num_resources = ARRAY_SIZE(i2c_emma_resources_1),
},
[2] = {
.name = I2C_EMMA2RH,
.id = 2,
.resource = i2c_emma_resources_2,
.num_resources = ARRAY_SIZE(i2c_emma_resources_2),
},
};
#define EMMA2RH_SERIAL_CLOCK 18544000
#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
static struct plat_serial8250_port platform_serial_ports[] = {
[0] = {
.membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
.mapbase = EMMA2RH_PFUR0_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR0,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
.iotype = UPIO_MEM,
.flags = EMMA2RH_SERIAL_FLAGS,
}, [1] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
.mapbase = EMMA2RH_PFUR1_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR1,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
.iotype = UPIO_MEM,
.flags = EMMA2RH_SERIAL_FLAGS,
}, [2] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
.mapbase = EMMA2RH_PFUR2_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR2,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
.iotype = UPIO_MEM,
.flags = EMMA2RH_SERIAL_FLAGS,
}, [3] = {
.flags = 0,
},
};
static struct platform_device serial_emma = {
.name = "serial8250",
.dev = {
.platform_data = &platform_serial_ports,
},
};
static struct mtd_partition markeins_parts[] = {
[0] = {
.name = "RootFS",
.offset = 0x00000000,
.size = 0x00c00000,
},
[1] = {
.name = "boot code area",
.offset = MTDPART_OFS_APPEND,
.size = 0x00100000,
},
[2] = {
.name = "kernel image",
.offset = MTDPART_OFS_APPEND,
.size = 0x00300000,
},
[3] = {
.name = "RootFS2",
.offset = MTDPART_OFS_APPEND,
.size = 0x00c00000,
},
[4] = {
.name = "boot code area2",
.offset = MTDPART_OFS_APPEND,
.size = 0x00100000,
},
[5] = {
.name = "kernel image2",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data markeins_flash_data = {
.width = 2,
.nr_parts = ARRAY_SIZE(markeins_parts),
.parts = markeins_parts
};
static struct resource markeins_flash_resource = {
.start = 0x1e000000,
.end = 0x02000000,
.flags = IORESOURCE_MEM
};
static struct platform_device markeins_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &markeins_flash_data,
},
.num_resources = 1,
.resource = &markeins_flash_resource,
};
static struct platform_device *devices[] = {
i2c_emma_devices,
i2c_emma_devices + 1,
i2c_emma_devices + 2,
&serial_emma,
&markeins_flash_device,
};
static int __init platform_devices_setup(void)
{
return platform_add_devices(devices, ARRAY_SIZE(devices));
}
arch_initcall(platform_devices_setup);

115
arch/mips/emma/markeins/setup.c
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@ -1,115 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c.
*
* Copyright 2001 MontaVista Software Inc.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/time.h>
#include <asm/reboot.h>
#include <asm/emma/emma2rh.h>
#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
extern void markeins_led(const char *);
static int bus_frequency;
static void markeins_machine_restart(char *command)
{
static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000;
printk("cannot EMMA2RH Mark-eins restart.\n");
markeins_led("restart.");
back_to_prom();
}
static void markeins_machine_halt(void)
{
printk("EMMA2RH Mark-eins halted.\n");
markeins_led("halted.");
while (1) ;
}
static void markeins_machine_power_off(void)
{
markeins_led("poweroff.");
while (1) ;
}
static unsigned long __initdata emma2rh_clock[4] = {
166500000, 187312500, 199800000, 210600000
};
static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
{
u32 reg;
/* detect from boot strap */
reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
reg = (reg >> 4) & 0x3;
return emma2rh_clock[reg];
}
void __init plat_time_init(void)
{
u32 reg;
if (bus_frequency == 0)
bus_frequency = detect_bus_frequency(0);
reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
if ((reg & 0x3) == 0)
reg = (reg >> 6) & 0x3;
else {
reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL);
reg = (reg >> 4) & 0x3;
}
mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
}
static void markeins_board_init(void);
extern void markeins_irq_setup(void);
static inline void __init markeins_sio_setup(void)
{
}
void __init plat_mem_setup(void)
{
/* initialize board - we don't trust the loader */
markeins_board_init();
set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
_machine_restart = markeins_machine_restart;
_machine_halt = markeins_machine_halt;
pm_power_off = markeins_machine_power_off;
/* setup resource limits */
ioport_resource.start = EMMA2RH_PCI_IO_BASE;
ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1;
iomem_resource.start = EMMA2RH_IO_BASE;
iomem_resource.end = EMMA2RH_ROM_BASE - 1;
markeins_sio_setup();
}
static void __init markeins_board_init(void)
{
u32 val;
val = emma2rh_in32(EMMA2RH_PBRD_INT_EN); /* open serial interrupts. */
emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa);
val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL); /* set serial clocks. */
emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5); /* 18MHz */
emma2rh_out32(EMMA2RH_PCI_CONTROL, 0);
markeins_led("MVL E2RH");
}

5
arch/mips/fw/cfe/cfe_api.c
View File

@ -243,11 +243,6 @@ int cfe_getfwinfo(cfe_fwinfo_t * info)
info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa;
info->fwi_bootarea_size =
xiocb.plist.xiocb_fwinfo.fwi_bootarea_size;
#if 0
info->fwi_reserved1 = xiocb.plist.xiocb_fwinfo.fwi_reserved1;
info->fwi_reserved2 = xiocb.plist.xiocb_fwinfo.fwi_reserved2;
info->fwi_reserved3 = xiocb.plist.xiocb_fwinfo.fwi_reserved3;
#endif
return 0;
}

1
arch/mips/generic/Platform
View File

@ -8,7 +8,6 @@
# option) any later version.
#
platform-$(CONFIG_MIPS_GENERIC) += generic/
cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic
load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb

2
arch/mips/include/asm/asm-eva.h
View File

@ -180,7 +180,7 @@
#define user_ld(reg, addr) kernel_lw(reg, addr)
#else
#define user_sd(reg, addr) kernel_sd(reg, addr)
#define user_ld(reg, addr) kernel_sd(reg, addr)
#define user_ld(reg, addr) kernel_ld(reg, addr)
#endif /* CONFIG_32BIT */
#endif /* CONFIG_EVA */

24
arch/mips/include/asm/asm.h
View File

@ -74,10 +74,15 @@ symbol: .insn
.globl symbol; \
symbol = value
#define PANIC(msg) \
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
#define ASM_PANIC(msg) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
PTR_LA a0, 8f; \
jal panic; \
9: b 9b; \
.set pop; \
@ -87,22 +92,17 @@ symbol = value
* Print formatted string
*/
#ifdef CONFIG_PRINTK
#define PRINT(string) \
#define ASM_PRINT(string) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
PTR_LA a0, 8f; \
jal printk; \
.set pop; \
TEXT(string)
#else
#define PRINT(string)
#define ASM_PRINT(string)
#endif
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
/*
* Stack alignment
*/
@ -202,7 +202,9 @@ symbol = value
#define LONG_SRA sra
#define LONG_SRAV srav
#ifdef __ASSEMBLY__
#define LONG .word
#endif
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
@ -225,7 +227,9 @@ symbol = value
#define LONG_SRA dsra
#define LONG_SRAV dsrav
#ifdef __ASSEMBLY__
#define LONG .dword
#endif
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3

18
arch/mips/include/asm/asmmacro.h
View File

@ -44,7 +44,8 @@
.endm
#endif
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
.macro local_irq_enable reg=t0
ei
irq_enable_hazard
@ -54,7 +55,7 @@
di
irq_disable_hazard
.endm
#else
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
@ -79,7 +80,7 @@
sw \reg, TI_PRE_COUNT($28)
#endif
.endm
#endif /* CONFIG_CPU_MIPSR2 */
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro fpu_save_16even thread tmp=t0
.set push
@ -131,7 +132,7 @@
.macro fpu_save_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
defined(CONFIG_CPU_MIPSR6)
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
sll \tmp, \status, 5
bgez \tmp, 10f
fpu_save_16odd \thread
@ -190,7 +191,7 @@
.macro fpu_restore_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
defined(CONFIG_CPU_MIPSR6)
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
sll \tmp, \status, 5
bgez \tmp, 10f # 16 register mode?
@ -200,16 +201,17 @@
fpu_restore_16even \thread \tmp
.endm
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
.macro _EXT rd, rs, p, s
ext \rd, \rs, \p, \s
.endm
#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro _EXT rd, rs, p, s
srl \rd, \rs, \p
andi \rd, \rd, (1 << \s) - 1
.endm
#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
/*
* Temporary until all gas have MT ASE support

13
arch/mips/include/asm/bootinfo.h
View File

@ -41,17 +41,6 @@
#define MACH_DS5800 9 /* DECsystem 5800 */
#define MACH_DS5900 10 /* DECsystem 5900 */
/*
* Valid machtype for group PMC-MSP
*/
#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */
#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
/*
* Valid machtype for group Mikrotik
*/
@ -121,7 +110,7 @@ extern unsigned long fw_passed_dtb;
#endif
/*
* Platform memory detection hook called by setup_arch
* Platform memory detection hook called by arch_mem_init()
*/
extern void plat_mem_setup(void);

3
arch/mips/include/asm/branch.h
View File

@ -27,6 +27,9 @@ extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
#define MM_POOL32A_MINOR_SHIFT 0x6
#define MM_MIPS32_COND_FC 0x30
int isBranchInstr(struct pt_regs *regs,
struct mm_decoded_insn dec_insn, unsigned long *contpc);
extern int __mm_isBranchInstr(struct pt_regs *regs,
struct mm_decoded_insn dec_insn, unsigned long *contpc);

2
arch/mips/include/asm/cacheops.h
View File

@ -48,7 +48,7 @@
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D (Cache_D | 0x0c)
#define Fill (Cache_I | 0x14)
#define Fill_I (Cache_I | 0x14)
#define Hit_Writeback_I (Cache_I | Hit_Writeback)
#define Hit_Writeback_D (Cache_D | Hit_Writeback)

49
arch/mips/include/asm/clock.h
View File

@ -1,49 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MIPS_CLOCK_H
#define __ASM_MIPS_CLOCK_H
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/clk.h>
struct clk;
struct clk_ops {
void (*init) (struct clk *clk);
void (*enable) (struct clk *clk);
void (*disable) (struct clk *clk);
void (*recalc) (struct clk *clk);
int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
long (*round_rate) (struct clk *clk, unsigned long rate);
};
struct clk {
struct list_head node;
const char *name;
int id;
struct module *owner;
struct clk *parent;
struct clk_ops *ops;
struct kref kref;
unsigned long rate;
unsigned long flags;
};
#define CLK_ALWAYS_ENABLED (1 << 0)
#define CLK_RATE_PROPAGATES (1 << 1)
int clk_init(void);
int __clk_enable(struct clk *);
void __clk_disable(struct clk *);
void clk_recalc_rate(struct clk *);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
#endif /* __ASM_MIPS_CLOCK_H */

5
arch/mips/include/asm/compiler.h
View File

@ -57,6 +57,11 @@
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
#define MIPS_ISA_LEVEL_RAW mips64r6
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
#elif defined(CONFIG_CPU_MIPSR5)
#define MIPS_ISA_LEVEL "mips64r5"
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
#define MIPS_ISA_LEVEL_RAW mips64r5
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
#else
/* MIPS64 is a superset of MIPS32 */
#define MIPS_ISA_LEVEL "mips64r2"

47
arch/mips/include/asm/cpu-features.h
View File

@ -284,14 +284,23 @@
#ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
#endif
#ifndef cpu_has_mips32r5
# define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
#endif
#ifndef cpu_has_mips32r6
# define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
#endif
#ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)
# define cpu_has_mips64r1 (cpu_has_64bits && \
__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
#endif
#ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)
# define cpu_has_mips64r2 (cpu_has_64bits && \
__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
#endif
#ifndef cpu_has_mips64r5
# define cpu_has_mips64r5 (cpu_has_64bits && \
__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
#endif
#ifndef cpu_has_mips64r6
# define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
@ -313,19 +322,25 @@
(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
#define cpu_has_mips_4_5_64_r2_r6 \
(cpu_has_mips_4_5 | cpu_has_mips64r1 | \
cpu_has_mips_r2 | cpu_has_mips_r6)
cpu_has_mips_r2 | cpu_has_mips_r5 | \
cpu_has_mips_r6)
#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips32r5 | cpu_has_mips32r6)
#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \
cpu_has_mips64r5 | cpu_has_mips64r6)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5)
#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips32r6 | cpu_has_mips64r1 | \
cpu_has_mips64r2 | cpu_has_mips64r6)
cpu_has_mips32r5 | cpu_has_mips32r6 | \
cpu_has_mips64r1 | cpu_has_mips64r2 | \
cpu_has_mips64r5 | cpu_has_mips64r6)
/* MIPSR2 and MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
/* MIPSR2 - MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \
cpu_has_mips_r6)
/*
* cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
@ -435,9 +450,6 @@
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 0
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 0
# endif
# ifndef cpu_vmbits
# define cpu_vmbits 31
# endif
@ -456,9 +468,6 @@
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 1
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 1
# endif
# ifndef cpu_vmbits
# define cpu_vmbits cpu_data[0].vmbits
# define __NEED_VMBITS_PROBE
@ -620,6 +629,14 @@
# endif
#endif
#ifndef cpu_has_mm_sysad
# define cpu_has_mm_sysad __opt(MIPS_CPU_MM_SYSAD)
#endif
#ifndef cpu_has_mm_full
# define cpu_has_mm_full __opt(MIPS_CPU_MM_FULL)
#endif
/*
* Guest capabilities
*/

11
arch/mips/include/asm/cpu-info.h
View File

@ -105,6 +105,15 @@ struct cpuinfo_mips {
unsigned int gtoffset_mask;
unsigned int guestid_mask;
unsigned int guestid_cache;
#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
/* CPUCFG data for this CPU, synthesized at probe time.
*
* CPUCFG select 0 is PRId, 4 and above are unimplemented for now.
* So the only stored values are for CPUCFG selects 1-3 inclusive.
*/
u32 loongson3_cpucfg_data[3];
#endif
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];
@ -142,7 +151,7 @@ struct proc_cpuinfo_notifier_args {
static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
{
/* Optimisation for systems where multiple clusters aren't used */
if (!IS_ENABLED(CONFIG_CPU_MIPSR6))
if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
return 0;
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>

7
arch/mips/include/asm/cpu-type.h
View File

@ -51,13 +51,18 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_M14KEC:
case CPU_INTERAPTIV:
case CPU_PROAPTIV:
case CPU_P5600:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R5
case CPU_M5150:
case CPU_P5600:
#endif
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R5) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R5) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R6)
case CPU_QEMU_GENERIC:
#endif

18
arch/mips/include/asm/cpu.h
View File

@ -250,6 +250,10 @@
#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON2K_R1_0 0x0000
#define PRID_REV_LOONGSON2K_R1_1 0x0001
#define PRID_REV_LOONGSON2K_R1_2 0x0002
#define PRID_REV_LOONGSON2K_R1_3 0x0003
#define PRID_REV_LOONGSON3A_R1 0x0005
#define PRID_REV_LOONGSON3B_R1 0x0006
#define PRID_REV_LOONGSON3B_R2 0x0007
@ -343,14 +347,16 @@ enum cpu_type_enum {
#define MIPS_CPU_ISA_M32R2 0x00000020
#define MIPS_CPU_ISA_M64R1 0x00000040
#define MIPS_CPU_ISA_M64R2 0x00000080
#define MIPS_CPU_ISA_M32R6 0x00000100
#define MIPS_CPU_ISA_M64R6 0x00000200
#define MIPS_CPU_ISA_M32R5 0x00000100
#define MIPS_CPU_ISA_M64R5 0x00000200
#define MIPS_CPU_ISA_M32R6 0x00000400
#define MIPS_CPU_ISA_M64R6 0x00000800
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
MIPS_CPU_ISA_M64R6)
MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6)
/*
* CPU Option encodings
@ -416,7 +422,9 @@ enum cpu_type_enum {
#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(58) /* CPU Only support MAC2008 Fused multiply-add instruction */
#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
/*
* CPU ASE encodings

248
arch/mips/include/asm/emma/emma2rh.h
View File

@ -1,248 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*/
#ifndef __ASM_EMMA_EMMA2RH_H
#define __ASM_EMMA_EMMA2RH_H
#include <irq.h>
/*
* EMMA2RH registers
*/
#define REGBASE 0x10000000
#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
#define EMMA2RH_PCI_INT (0x200020+REGBASE)
#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
/* the actual ram size is detected at run-time */
#define EMMA2RH_RAM_BASE 0x00000000
#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */
#define EMMA2RH_IO_BASE 0x10000000
#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_GENERALIO_BASE 0x11000000
#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_PCI_IO_BASE 0x12000000
#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define EMMA2RH_PCI_MEM_BASE 0x14000000
#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define EMMA2RH_ROM_BASE 0x1c000000
#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */
#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
#define NUM_EMMA2RH_IRQ 96
#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/*
* emma2rh irq defs
*/
#define EMMA2RH_IRQ_INT(n) (EMMA2RH_IRQ_BASE + (n))
#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT(49)
#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT(50)
#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT(51)
#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT(56)
#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT(57)
#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT(58)
/*
* EMMA2RH Register Access
*/
#define EMMA2RH_BASE (0xa0000000)
static inline void emma2rh_sync(void)
{
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
}
static inline void emma2rh_out32(u32 offset, u32 val)
{
*(volatile u32 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u32 emma2rh_in32(u32 offset)
{
u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
return val;
}
static inline void emma2rh_out16(u32 offset, u16 val)
{
*(volatile u16 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u16 emma2rh_in16(u32 offset)
{
u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
return val;
}
static inline void emma2rh_out8(u32 offset, u8 val)
{
*(volatile u8 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u8 emma2rh_in8(u32 offset)
{
u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
return val;
}
/**
* IIC registers map
**/
/*---------------------------------------------------------------------------*/
/* CNT - Control register (00H R/W) */
/*---------------------------------------------------------------------------*/
#define SPT 0x00000001
#define STT 0x00000002
#define ACKE 0x00000004
#define WTIM 0x00000008
#define SPIE 0x00000010
#define WREL 0x00000020
#define LREL 0x00000040
#define IICE 0x00000080
#define CNT_RESERVED 0x000000ff /* reserved bit 0 */
#define I2C_EMMA_START (IICE | STT)
#define I2C_EMMA_STOP (IICE | SPT)
#define I2C_EMMA_REPSTART I2C_EMMA_START
/*---------------------------------------------------------------------------*/
/* STA - Status register (10H Read) */
/*---------------------------------------------------------------------------*/
#define MSTS 0x00000080
#define ALD 0x00000040
#define EXC 0x00000020
#define COI 0x00000010
#define TRC 0x00000008
#define ACKD 0x00000004
#define STD 0x00000002
#define SPD 0x00000001
/*---------------------------------------------------------------------------*/
/* CSEL - Clock select register (20H R/W) */
/*---------------------------------------------------------------------------*/
#define FCL 0x00000080
#define ND50 0x00000040
#define CLD 0x00000020
#define DAD 0x00000010
#define SMC 0x00000008
#define DFC 0x00000004
#define CL 0x00000003
#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */
#define FAST397 0x0000008b
#define FAST297 0x0000008a
#define FAST347 0x0000000b
#define FAST260 0x0000000a
#define FAST130 0x00000008
#define STANDARD108 0x00000083
#define STANDARD83 0x00000082
#define STANDARD95 0x00000003
#define STANDARD73 0x00000002
#define STANDARD36 0x00000001
#define STANDARD71 0x00000000
/*---------------------------------------------------------------------------*/
/* SVA - Slave address register (30H R/W) */
/*---------------------------------------------------------------------------*/
#define SVA 0x000000fe
/*---------------------------------------------------------------------------*/
/* SHR - Shift register (40H R/W) */
/*---------------------------------------------------------------------------*/
#define SR 0x000000ff
/*---------------------------------------------------------------------------*/
/* INT - Interrupt register (50H R/W) */
/* INTM - Interrupt mask register (60H R/W) */
/*---------------------------------------------------------------------------*/
#define INTE0 0x00000001
/***********************************************************************
* I2C registers
***********************************************************************
*/
#define I2C_EMMA_CNT 0x00
#define I2C_EMMA_STA 0x10
#define I2C_EMMA_CSEL 0x20
#define I2C_EMMA_SVA 0x30
#define I2C_EMMA_SHR 0x40
#define I2C_EMMA_INT 0x50
#define I2C_EMMA_INTM 0x60
/*
* include the board dependent part
*/
#ifdef CONFIG_NEC_MARKEINS
#include <asm/emma/markeins.h>
#else
#error "Unknown EMMA2RH board!"
#endif
#endif /* __ASM_EMMA_EMMA2RH_H */

28
arch/mips/include/asm/emma/markeins.h
View File

@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*/
#ifndef MARKEINS_H
#define MARKEINS_H
#define NUM_EMMA2RH_IRQ_SW 32
#define NUM_EMMA2RH_IRQ_GPIO 32
#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
#define EMMA2RH_SW_IRQ_INT(n) (EMMA2RH_SW_IRQ_BASE + (n))
#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17
#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18
#endif /* CONFIG_MARKEINS */

6
arch/mips/include/asm/fpu.h
View File

@ -71,12 +71,12 @@ static inline int __enable_fpu(enum fpu_mode mode)
goto fr_common;
case FPU_64BIT:
#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
|| defined(CONFIG_64BIT))
#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_64BIT))
/* we only have a 32-bit FPU */
return SIGFPE;
#endif
/* fall through */
fallthrough;
case FPU_32BIT:
if (cpu_has_fre) {
/* clear FRE */

4
arch/mips/include/asm/fpu_emulator.h
View File

@ -172,10 +172,6 @@ void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
struct task_struct *tsk);
int process_fpemu_return(int sig, void __user *fault_addr,
unsigned long fcr31);
int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
unsigned long *contpc);
int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
unsigned long *contpc);
/*
* Mask the FCSR Cause bits according to the Enable bits, observing

8
arch/mips/include/asm/hazards.h
View File

@ -22,8 +22,9 @@
/*
* TLB hazards
*/
#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)) && \
!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
/*
* MIPSR2 defines ehb for hazard avoidance
@ -278,7 +279,8 @@ do { \
#define __disable_fpu_hazard
#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
#define __enable_fpu_hazard \
___ehb

87
arch/mips/include/asm/io.h
View File

@ -30,8 +30,6 @@
#include <asm/pgtable-bits.h>
#include <asm/processor.h>
#include <asm/string.h>
#include <ioremap.h>
#include <mangle-port.h>
/*
@ -153,66 +151,9 @@ static inline void *isa_bus_to_virt(unsigned long address)
*/
#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
extern void __iounmap(const volatile void __iomem *addr);
static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
void __iomem *addr = plat_ioremap(offset, size, flags);
if (addr)
return addr;
#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
if (cpu_has_64bit_addresses) {
u64 base = UNCAC_BASE;
/*
* R10000 supports a 2 bit uncached attribute therefore
* UNCAC_BASE may not equal IO_BASE.
*/
if (flags == _CACHE_UNCACHED)
base = (u64) IO_BASE;
return (void __iomem *) (unsigned long) (base + offset);
} else if (__builtin_constant_p(offset) &&
__builtin_constant_p(size) && __builtin_constant_p(flags)) {
phys_addr_t phys_addr, last_addr;
phys_addr = fixup_bigphys_addr(offset, size);
/* Don't allow wraparound or zero size. */
last_addr = phys_addr + size - 1;
if (!size || last_addr < phys_addr)
return NULL;
/*
* Map uncached objects in the low 512MB of address
* space using KSEG1.
*/
if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
flags == _CACHE_UNCACHED)
return (void __iomem *)
(unsigned long)CKSEG1ADDR(phys_addr);
}
return __ioremap(offset, size, flags);
#undef __IS_LOW512
}
/*
* ioremap_prot - map bus memory into CPU space
* @offset: bus address of the memory
* @size: size of the resource to map
* ioremap_prot gives the caller control over cache coherency attributes (CCA)
*/
static inline void __iomem *ioremap_prot(phys_addr_t offset,
unsigned long size, unsigned long prot_val) {
return __ioremap_mode(offset, size, prot_val & _CACHE_MASK);
}
void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
unsigned long prot_val);
void iounmap(const volatile void __iomem *addr);
/*
* ioremap - map bus memory into CPU space
@ -226,7 +167,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset,
* address.
*/
#define ioremap(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
ioremap_prot((offset), (size), _CACHE_UNCACHED)
#define ioremap_uc ioremap
/*
@ -245,7 +186,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset,
* memory-like regions on I/O busses.
*/
#define ioremap_cache(offset, size) \
__ioremap_mode((offset), (size), _page_cachable_default)
ioremap_prot((offset), (size), _page_cachable_default)
/*
* ioremap_wc - map bus memory into CPU space
@ -266,23 +207,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset,
* _CACHE_UNCACHED option (see cpu_probe() method).
*/
#define ioremap_wc(offset, size) \
__ioremap_mode((offset), (size), boot_cpu_data.writecombine)
static inline void iounmap(const volatile void __iomem *addr)
{
if (plat_iounmap(addr))
return;
#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
if (cpu_has_64bit_addresses ||
(__builtin_constant_p(addr) && __IS_KSEG1(addr)))
return;
__iounmap(addr);
#undef __IS_KSEG1
}
ioremap_prot((offset), (size), boot_cpu_data.writecombine)
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
#define war_io_reorder_wmb() wmb()

19
arch/mips/include/asm/lasat/ds1603.h
View File

@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/addrspace.h>
/* Lasat 100 */
#define DS1603_REG_100 (KSEG1ADDR(0x1c810000))
#define DS1603_RST_100 (1 << 2)
#define DS1603_CLK_100 (1 << 0)
#define DS1603_DATA_SHIFT_100 1
#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100)
/* Lasat 200 */
#define DS1603_REG_200 (KSEG1ADDR(0x11000000))
#define DS1603_RST_200 (1 << 3)
#define DS1603_CLK_200 (1 << 4)
#define DS1603_DATA_200 (1 << 5)
#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000)
#define DS1603_DATA_READ_SHIFT_200 9
#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200)

18
arch/mips/include/asm/lasat/eeprom.h
View File

@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/addrspace.h>
/* lasat 100 */
#define AT93C_REG_100 KSEG1ADDR(0x1c810000)
#define AT93C_RDATA_REG_100 AT93C_REG_100
#define AT93C_RDATA_SHIFT_100 4
#define AT93C_WDATA_SHIFT_100 4
#define AT93C_CS_M_100 (1 << 5)
#define AT93C_CLK_M_100 (1 << 3)
/* lasat 200 */
#define AT93C_REG_200 KSEG1ADDR(0x11000000)
#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000)
#define AT93C_RDATA_SHIFT_200 8
#define AT93C_WDATA_SHIFT_200 2
#define AT93C_CS_M_200 (1 << 0)
#define AT93C_CLK_M_200 (1 << 1)

23
arch/mips/include/asm/lasat/head.h
View File

@ -1,23 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Image header stuff
*/
#ifndef _HEAD_H
#define _HEAD_H
#define LASAT_K_MAGIC0_VAL 0xfedeabba
#define LASAT_K_MAGIC1_VAL 0x00bedead
#ifndef _LANGUAGE_ASSEMBLY
#include <linux/types.h>
struct bootloader_header {
u32 magic[2];
u32 version;
u32 image_start;
u32 image_size;
u32 kernel_start;
u32 kernel_entry;
};
#endif
#endif /* _HEAD_H */

245
arch/mips/include/asm/lasat/lasat.h
View File

@ -1,245 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* lasat.h
*
* Thomas Horsten <thh@lasat.com>
* Copyright (C) 2000 LASAT Networks A/S.
*
* Configuration for LASAT boards, loads the appropriate include files.
*/
#ifndef _LASAT_H
#define _LASAT_H
#ifndef _LANGUAGE_ASSEMBLY
extern struct lasat_misc {
volatile u32 *reset_reg;
volatile u32 *flash_wp_reg;
u32 flash_wp_bit;
} *lasat_misc;
enum lasat_mtdparts {
LASAT_MTD_BOOTLOADER,
LASAT_MTD_SERVICE,
LASAT_MTD_NORMAL,
LASAT_MTD_CONFIG,
LASAT_MTD_FS,
LASAT_MTD_LAST
};
/*
* The format of the data record in the EEPROM.
* See the LASAT Hardware Configuration field specification for a detailed
* description of the config field.
*/
#include <linux/types.h>
#define LASAT_EEPROM_VERSION 7
struct lasat_eeprom_struct {
unsigned int version;
unsigned int cfg[3];
unsigned char hwaddr[6];
unsigned char print_partno[12];
unsigned char term0;
unsigned char print_serial[14];
unsigned char term1;
unsigned char prod_partno[12];
unsigned char term2;
unsigned char prod_serial[14];
unsigned char term3;
unsigned char passwd_hash[16];
unsigned char pwdnull;
unsigned char vendid;
unsigned char ts_ref;
unsigned char ts_signoff;
unsigned char reserved[11];
unsigned char debugaccess;
unsigned short prid;
unsigned int serviceflag;
unsigned int ipaddr;
unsigned int netmask;
unsigned int crc32;
};
struct lasat_eeprom_struct_pre7 {
unsigned int version;
unsigned int flags[3];
unsigned char hwaddr0[6];
unsigned char hwaddr1[6];
unsigned char print_partno[9];
unsigned char term0;
unsigned char print_serial[14];
unsigned char term1;
unsigned char prod_partno[9];
unsigned char term2;
unsigned char prod_serial[14];
unsigned char term3;
unsigned char passwd_hash[24];
unsigned char pwdnull;
unsigned char vendor;
unsigned char ts_ref;
unsigned char ts_signoff;
unsigned char reserved[6];
unsigned int writecount;
unsigned int ipaddr;
unsigned int netmask;
unsigned int crc32;
};
/* Configuration descriptor encoding - see the doc for details */
#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf)
#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf)
#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf)
#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf)
#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf)
#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf)
#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf)
#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf)
#define LASAT_W1_EDHAC(v) (((v)) & 0xf)
#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1)
#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1)
#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1)
#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1)
#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1)
#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1)
#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1)
#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf)
#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf)
#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf)
#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf)
#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf)
/* Routines specific to LASAT boards */
#define LASAT_BMID_MASQUERADE2 0
#define LASAT_BMID_MASQUERADEPRO 1
#define LASAT_BMID_SAFEPIPE25 2
#define LASAT_BMID_SAFEPIPE50 3
#define LASAT_BMID_SAFEPIPE100 4
#define LASAT_BMID_SAFEPIPE5000 5
#define LASAT_BMID_SAFEPIPE7000 6
#define LASAT_BMID_SAFEPIPE1000 7
#if 0
#define LASAT_BMID_SAFEPIPE30 7
#define LASAT_BMID_SAFEPIPE5100 8
#define LASAT_BMID_SAFEPIPE7100 9
#endif
#define LASAT_BMID_UNKNOWN 0xf
#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */
#define LASAT_HAS_EDHAC (1 << 0)
#define LASAT_EDHAC_FAST (1 << 1)
#define LASAT_HAS_EADI (1 << 2)
#define LASAT_HAS_HIFN (1 << 3)
#define LASAT_HAS_ISDN (1 << 4)
#define LASAT_HAS_LEASEDLINE_IF (1 << 5)
#define LASAT_HAS_HDC (1 << 6)
#define LASAT_PRID_MASQUERADE2 0
#define LASAT_PRID_MASQUERADEPRO 1
#define LASAT_PRID_SAFEPIPE25 2
#define LASAT_PRID_SAFEPIPE50 3
#define LASAT_PRID_SAFEPIPE100 4
#define LASAT_PRID_SAFEPIPE5000 5
#define LASAT_PRID_SAFEPIPE7000 6
#define LASAT_PRID_SAFEPIPE30 7
#define LASAT_PRID_SAFEPIPE5100 8
#define LASAT_PRID_SAFEPIPE7100 9
#define LASAT_PRID_SAFEPIPE1110 10
#define LASAT_PRID_SAFEPIPE3020 11
#define LASAT_PRID_SAFEPIPE3030 12
#define LASAT_PRID_SAFEPIPE5020 13
#define LASAT_PRID_SAFEPIPE5030 14
#define LASAT_PRID_SAFEPIPE1120 15
#define LASAT_PRID_SAFEPIPE1130 16
#define LASAT_PRID_SAFEPIPE6010 17
#define LASAT_PRID_SAFEPIPE6110 18
#define LASAT_PRID_SAFEPIPE6210 19
#define LASAT_PRID_SAFEPIPE1020 20
#define LASAT_PRID_SAFEPIPE1040 21
#define LASAT_PRID_SAFEPIPE1060 22
struct lasat_info {
unsigned int li_cpu_hz;
unsigned int li_bus_hz;
unsigned int li_bmid;
unsigned int li_memsize;
unsigned int li_flash_size;
unsigned int li_prid;
unsigned char li_bmstr[16];
unsigned char li_namestr[32];
unsigned char li_typestr[16];
/* Info on the Flash layout */
unsigned int li_flash_base;
unsigned long li_flashpart_base[LASAT_MTD_LAST];
unsigned long li_flashpart_size[LASAT_MTD_LAST];
struct lasat_eeprom_struct li_eeprom_info;
unsigned int li_eeprom_upgrade_version;
unsigned int li_debugaccess;
};
extern struct lasat_info lasat_board_info;
static inline unsigned long lasat_flash_partition_start(int partno)
{
if (partno < 0 || partno >= LASAT_MTD_LAST)
return 0;
return lasat_board_info.li_flashpart_base[partno];
}
static inline unsigned long lasat_flash_partition_size(int partno)
{
if (partno < 0 || partno >= LASAT_MTD_LAST)
return 0;
return lasat_board_info.li_flashpart_size[partno];
}
/* Called from setup() to initialize the global board_info struct */
extern int lasat_init_board_info(void);
/* Write the modified EEPROM info struct */
extern void lasat_write_eeprom_info(void);
#define N_MACHTYPES 2
/* for calibration of delays */
/* the lasat_ndelay function is necessary because it is used at an
* early stage of the boot process where ndelay is not calibrated.
* It is used for the bit-banging rtc and eeprom drivers */
#include <linux/delay.h>
#include <linux/smp.h>
/* calculating with the slowest board with 100 MHz clock */
#define LASAT_100_DIVIDER 20
/* All 200's run at 250 MHz clock */
#define LASAT_200_DIVIDER 8
extern unsigned int lasat_ndelay_divider;
static inline void lasat_ndelay(unsigned int ns)
{
__delay(ns / lasat_ndelay_divider);
}
#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000)
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba
/* Lasat 100 boards */
#define LASAT_GT_BASE (KSEG1ADDR(0x14000000))
/* Lasat 200 boards */
#define Vrc5074_PHYS_BASE 0x1fa00000
#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE))
#define PCI_WINDOW1 0x1a000000
#endif /* _LASAT_H */

15
arch/mips/include/asm/lasat/lasatint.h
View File

@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_LASAT_LASATINT_H
#define __ASM_LASAT_LASATINT_H
/* lasat 100 */
#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
#define LASATINT_MASK_SHIFT_100 0
/* lasat 200 */
#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c))
#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
#define LASATINT_MASK_SHIFT_200 16
#endif /* __ASM_LASAT_LASATINT_H */

16
arch/mips/include/asm/lasat/picvue.h
View File

@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Lasat 100 */
#define PVC_REG_100 KSEG1ADDR(0x1c820000)
#define PVC_DATA_SHIFT_100 0
#define PVC_DATA_M_100 0xFF
#define PVC_E_100 (1 << 8)
#define PVC_RW_100 (1 << 9)
#define PVC_RS_100 (1 << 10)
/* Lasat 200 */
#define PVC_REG_200 KSEG1ADDR(0x11000000)
#define PVC_DATA_SHIFT_200 24
#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200)
#define PVC_E_200 (1 << 16)
#define PVC_RW_200 (1 << 17)
#define PVC_RS_200 (1 << 18)

14
arch/mips/include/asm/lasat/serial.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/lasat/lasat.h>
/* Lasat 100 boards serial configuration */
#define LASAT_BASE_BAUD_100 (7372800 / 16)
#define LASAT_UART_REGS_BASE_100 0x1c8b0000
#define LASAT_UART_REGS_SHIFT_100 2
#define LASATINT_UART_100 16
/* * LASAT 200 boards serial configuration */
#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
#define LASAT_UART_REGS_SHIFT_200 3
#define LASATINT_UART_200 21

17
arch/mips/include/asm/maar.h
View File

@ -32,7 +32,7 @@ unsigned platform_maar_init(unsigned num_pairs);
* @upper: The highest address that the MAAR pair will affect. Must be
* aligned to one byte before a 2^16 byte boundary.
* @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
* MIPS_MAAR_VL attribute will automatically be set.
* MIPS_MAAR_VL/MIPS_MAAR_VH attributes will automatically be set.
*
* Program the pair of MAAR registers specified by idx to apply the attributes
* specified by attrs to the range of addresses from lower to higher.
@ -48,17 +48,30 @@ static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
/* Automatically set MIPS_MAAR_VL */
attrs |= MIPS_MAAR_VL;
/* Write the upper address & attributes (only MIPS_MAAR_VL matters) */
/*
* Write the upper address & attributes (both MIPS_MAAR_VL and
* MIPS_MAAR_VH matter)
*/
write_c0_maari(idx << 1);
back_to_back_c0_hazard();
write_c0_maar(((upper >> 4) & MIPS_MAAR_ADDR) | attrs);
back_to_back_c0_hazard();
#ifdef CONFIG_XPA
upper >>= MIPS_MAARX_ADDR_SHIFT;
writex_c0_maar(((upper >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
back_to_back_c0_hazard();
#endif
/* Write the lower address & attributes */
write_c0_maari((idx << 1) | 0x1);
back_to_back_c0_hazard();
write_c0_maar((lower >> 4) | attrs);
back_to_back_c0_hazard();
#ifdef CONFIG_XPA
lower >>= MIPS_MAARX_ADDR_SHIFT;
writex_c0_maar(((lower >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
back_to_back_c0_hazard();
#endif
}
/**

1
arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
View File

@ -56,6 +56,5 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */

1
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
View File

@ -45,7 +45,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32

38
arch/mips/include/asm/mach-au1x00/ioremap.h
View File

@ -1,38 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/mach-au1x00/ioremap.h
*/
#ifndef __ASM_MACH_AU1X00_IOREMAP_H
#define __ASM_MACH_AU1X00_IOREMAP_H
#include <linux/types.h>
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);
#else
static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
#endif
/*
* Allow physical addresses to be fixed up to help 36-bit peripherals.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return __fixup_bigphys_addr(phys_addr, size);
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
return NULL;
}
static inline int plat_iounmap(const volatile void __iomem *addr)
{
return 0;
}
#endif /* __ASM_MACH_AU1X00_IOREMAP_H */

6
arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
View File

@ -13,16 +13,16 @@ static inline unsigned long bcm63xx_gpio_count(void)
case BCM6328_CPU_ID:
return 32;
case BCM3368_CPU_ID:
case BCM6358_CPU_ID:
return 40;
case BCM6338_CPU_ID:
return 8;
case BCM6345_CPU_ID:
return 16;
case BCM6362_CPU_ID:
return 48;
case BCM6358_CPU_ID:
case BCM6368_CPU_ID:
return 38;
case BCM6362_CPU_ID:
return 48;
case BCM6348_CPU_ID:
default:
return 37;

4
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
View File

@ -1367,8 +1367,8 @@
#define MISC_STRAPBUS_6328_REG 0x240
#define STRAPBUS_6328_FCVO_SHIFT 7
#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 18)
#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 18)
/*************************************************************************
* _REG relative to RSET_PCIE

5
arch/mips/include/asm/mach-bcm63xx/ioremap.h
View File

@ -4,11 +4,6 @@
#include <bcm63xx_cpu.h>
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
{
switch (bcm63xx_get_cpu_id()) {

5
arch/mips/include/asm/mach-bmips/ioremap.h
View File

@ -4,11 +4,6 @@
#include <linux/types.h>
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline int is_bmips_internal_registers(phys_addr_t offset)
{
if (offset >= 0xfff80000)

15
arch/mips/include/asm/mach-emma2rh/irq.h
View File

@ -1,15 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_EMMA2RH_IRQ_H
#define __ASM_MACH_EMMA2RH_IRQ_H
#define NR_IRQS 256
#include <asm/mach-generic/irq.h>
#endif /* __ASM_MACH_EMMA2RH_IRQ_H */

9
arch/mips/include/asm/mach-generic/ioremap.h
View File

@ -7,15 +7,6 @@
#include <linux/types.h>
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{

6
arch/mips/include/asm/mach-generic/irq.h
View File

@ -36,10 +36,4 @@
#endif /* CONFIG_IRQ_MIPS_CPU */
#ifdef CONFIG_MIPS_GIC
#ifndef MIPS_GIC_IRQ_BASE
#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
#endif
#endif /* CONFIG_MIPS_GIC */
#endif /* __ASM_MACH_GENERIC_IRQ_H */

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