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Second Round of Renesas ARM Based SoC DT Updates for v4.14

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* Use newly added Gen-3 fallback compat string
 
   This is consistent with ongoing efforts to use per-generation
   fallback strings where appropriate across devices found
   on R-Car SoCs. The aim of the effort being to strike a balance
   between the limited information available about the compatibility
   of devices found on different SoCs and the desire to ease enabling
   devices on new SoCs.
 
   This has no run-time effect due to the presence of a per-SoC
   compat string.
 
 * Enable second CPU core on RZ/G1M (r8a7743)
 
   The RZ/G1M has two CA15 cores running at up to 1.5GHz
 
 * Enable frequency scaling on RZ/G1M (r8a7743)
 
 * Add six I2C cores to RZ/G1M (r8a7743) SoC DT
 
   This is a step towards enabling these cores on boards that use this SoC
 
 * Add CEC clock for HDMI transmitter to R-Car M2-W (r8a7791) Koelsch
 
   Hans Verkuil says "The adv7511 on the Koelsch board has a 12 MHz fixed
   clock for the CEC block. Specify this in the dts to enable CEC support."
 
 * Add PFC support to RZ/G1E (r8a7745) SoC and add Ethernet and SCIF2
   pins to SK-RZG1E board.
 
   This allows the kernel to control multiplexed pins for Ethernet
   and SCIF2 rather than relying on setup inherited at boot.
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Merge tag 'renesas-dt2-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.14" from Simon Horman:

* Use newly added Gen-3 fallback compat string

  This is consistent with ongoing efforts to use per-generation
  fallback strings where appropriate across devices found
  on R-Car SoCs. The aim of the effort being to strike a balance
  between the limited information available about the compatibility
  of devices found on different SoCs and the desire to ease enabling
  devices on new SoCs.

  This has no run-time effect due to the presence of a per-SoC
  compat string.

* Enable second CPU core on RZ/G1M (r8a7743)

  The RZ/G1M has two CA15 cores running at up to 1.5GHz

* Enable frequency scaling on RZ/G1M (r8a7743)

* Add six I2C cores to RZ/G1M (r8a7743) SoC DT

  This is a step towards enabling these cores on boards that use this SoC

* Add CEC clock for HDMI transmitter to R-Car M2-W (r8a7791) Koelsch

  Hans Verkuil says "The adv7511 on the Koelsch board has a 12 MHz fixed
  clock for the CEC block. Specify this in the dts to enable CEC support."

* Add PFC support to RZ/G1E (r8a7745) SoC and add Ethernet and SCIF2
  pins to SK-RZG1E board.

  This allows the kernel to control multiplexed pins for Ethernet
  and SCIF2 rather than relying on setup inherited at boot.

* tag 'renesas-dt2-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r8a7791: Use R-Car SATA Gen2 fallback compat string
  ARM: dts: r8a7790: Use R-Car SATA Gen2 fallback compat string
  ARM: dts: r8a7743: Add OPP table for frequency scaling
  ARM: dts: r8a7743: Add APMU node and second CPU core
  ARM: dts: koelsch: Add CEC clock for HDMI transmitter
  ARM: dts: sk-rzg1e: add Ether pins
  ARM: dts: sk-rzg1e: add SCIF2 pins
  ARM: dts: r8a7745: add PFC support
  ARM: dts: r8a7743: Add I2C DT support
This commit is contained in:
Arnd Bergmann 2017-08-18 23:10:31 +02:00
commit 81f794d701
6 changed files with 164 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

122
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -18,9 +18,19 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -28,8 +38,26 @@
reg = <0>;
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
<1312500 1000000>,
<1125000 1000000>,
< 937500 1000000>,
< 750000 1000000>,
< 375000 1000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
};
L2_CA15: cache-controller-0 {
@ -48,6 +76,12 @@
#size-cells = <2>;
ranges;
apmu@e6152000 {
compatible = "renesas,r8a7743-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -314,6 +348,94 @@
dma-channels = <15>;
};
/* The memory map in the User's Manual maps the cores to bus
* numbers
*/
i2c0: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7743",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 931>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c1: i2c@e6518000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7743",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6518000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 930>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6530000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7743",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6530000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 929>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e6540000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7743",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6540000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 928>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c4: i2c@e6520000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7743",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6520000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 927>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c5: i2c@e6528000 {
/* doesn't need pinmux */
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7743",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 925>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 925>;
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7743",
"renesas,rcar-gen2-scifa", "renesas,scifa";

25
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for the SK-RZG1E board
*
* Copyright (C) 2016 Cogent Embedded, Inc.
* Copyright (C) 2016-2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@ -34,11 +34,34 @@
clock-frequency = <20000000>;
};
&pfc {
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
ether_pins: ether {
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
groups = "intc_irq8";
function = "intc";
};
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";

7
arch/arm/boot/dts/r8a7745.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7745 SoC
*
* Copyright (C) 2016 Cogent Embedded Inc.
* Copyright (C) 2016-2017 Cogent Embedded Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@ -123,6 +123,11 @@
#power-domain-cells = <1>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7745";
reg = <0 0xe6060000 0 0x11c>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";

4
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -873,7 +873,7 @@
};
sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7790";
compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
@ -882,7 +882,7 @@
};
sata1: sata@ee500000 {
compatible = "renesas,sata-r8a7790";
compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
reg = <0 0xee500000 0 0x2000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;

8
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -642,11 +642,19 @@
};
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cec_clock>;
clock-names = "cec";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";

4
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -933,7 +933,7 @@
};
sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7791";
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
@ -942,7 +942,7 @@
};
sata1: sata@ee500000 {
compatible = "renesas,sata-r8a7791";
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0 0xee500000 0 0x2000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;