forked from Minki/linux
[PATCH] libata: use new SCR and on/offline functions
Use new SCR and on/offline functions. Note that for LLDD which know it implements SCR callbacks, SCR functions are guaranteed to succeed and ata_port_online() == !ata_port_offline(). Signed-off-by: Tejun Heo <htejun@gmail.com>
This commit is contained in:
Tejun Heo
parent
34bf21704c
commit
81952c5497
@ -567,7 +567,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
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DPRINTK("ENTER\n");
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if (!sata_dev_present(ap)) {
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if (ata_port_offline(ap)) {
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DPRINTK("PHY reports no device\n");
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*class = ATA_DEV_NONE;
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return 0;
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@ -640,7 +640,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
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msleep(150);
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*class = ATA_DEV_NONE;
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if (sata_dev_present(ap)) {
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if (ata_port_online(ap)) {
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if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
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rc = -EIO;
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reason = "device not ready";
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@ -670,7 +670,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
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rc = sata_std_hardreset(ap, class);
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ahci_start_engine(ap);
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if (rc == 0 && sata_dev_present(ap))
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if (rc == 0 && ata_port_online(ap))
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*class = ahci_dev_classify(ap);
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if (*class == ATA_DEV_UNKNOWN)
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*class = ATA_DEV_NONE;
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@ -1494,13 +1494,11 @@ static void sata_print_link_status(struct ata_port *ap)
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{
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u32 sstatus, scontrol, tmp;
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if (!ap->ops->scr_read)
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if (sata_scr_read(ap, SCR_STATUS, &sstatus))
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return;
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sata_scr_read(ap, SCR_CONTROL, &scontrol);
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sstatus = scr_read(ap, SCR_STATUS);
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scontrol = scr_read(ap, SCR_CONTROL);
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if (sata_dev_present(ap)) {
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if (ata_port_online(ap)) {
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tmp = (sstatus >> 4) & 0xf;
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printk(KERN_INFO
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"ata%u: SATA link up %s (SStatus %X SControl %X)\n",
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@ -1531,17 +1529,18 @@ void __sata_phy_reset(struct ata_port *ap)
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if (ap->flags & ATA_FLAG_SATA_RESET) {
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/* issue phy wake/reset */
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scr_write_flush(ap, SCR_CONTROL, 0x301);
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sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
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/* Couldn't find anything in SATA I/II specs, but
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* AHCI-1.1 10.4.2 says at least 1 ms. */
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mdelay(1);
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}
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scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
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/* phy wake/clear reset */
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sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
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/* wait for phy to become ready, if necessary */
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do {
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msleep(200);
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sstatus = scr_read(ap, SCR_STATUS);
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sata_scr_read(ap, SCR_STATUS, &sstatus);
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if ((sstatus & 0xf) != 1)
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break;
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} while (time_before(jiffies, timeout));
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@ -1550,7 +1549,7 @@ void __sata_phy_reset(struct ata_port *ap)
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sata_print_link_status(ap);
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/* TODO: phy layer with polling, timeouts, etc. */
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if (sata_dev_present(ap))
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if (!ata_port_offline(ap))
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ata_port_probe(ap);
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else
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ata_port_disable(ap);
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@ -1638,11 +1637,12 @@ void ata_port_disable(struct ata_port *ap)
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*/
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int sata_down_spd_limit(struct ata_port *ap)
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{
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u32 spd, mask;
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int highbit;
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u32 sstatus, spd, mask;
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int rc, highbit;
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if (ap->cbl != ATA_CBL_SATA || !ap->ops->scr_read)
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return -EOPNOTSUPP;
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rc = sata_scr_read(ap, SCR_STATUS, &sstatus);
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if (rc)
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return rc;
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mask = ap->sata_spd_limit;
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if (mask <= 1)
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@ -1650,7 +1650,7 @@ int sata_down_spd_limit(struct ata_port *ap)
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highbit = fls(mask) - 1;
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mask &= ~(1 << highbit);
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spd = (scr_read(ap, SCR_STATUS) >> 4) & 0xf;
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spd = (sstatus >> 4) & 0xf;
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if (spd <= 1)
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return -EINVAL;
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spd--;
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@ -1700,11 +1700,9 @@ int sata_set_spd_needed(struct ata_port *ap)
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{
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u32 scontrol;
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if (ap->cbl != ATA_CBL_SATA || !ap->ops->scr_read)
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if (sata_scr_read(ap, SCR_CONTROL, &scontrol))
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return 0;
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scontrol = scr_read(ap, SCR_CONTROL);
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return __sata_set_spd_needed(ap, &scontrol);
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}
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@ -1719,20 +1717,22 @@ int sata_set_spd_needed(struct ata_port *ap)
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*
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* RETURNS:
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* 0 if spd doesn't need to be changed, 1 if spd has been
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* changed. -EOPNOTSUPP if SCR registers are inaccessible.
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* changed. Negative errno if SCR registers are inaccessible.
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*/
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int sata_set_spd(struct ata_port *ap)
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{
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u32 scontrol;
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int rc;
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if (ap->cbl != ATA_CBL_SATA || !ap->ops->scr_read)
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return -EOPNOTSUPP;
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if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
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return rc;
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scontrol = scr_read(ap, SCR_CONTROL);
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if (!__sata_set_spd_needed(ap, &scontrol))
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return 0;
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scr_write(ap, SCR_CONTROL, scontrol);
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if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
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return rc;
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return 1;
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}
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@ -2336,20 +2336,26 @@ static int sata_phy_resume(struct ata_port *ap)
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{
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unsigned long timeout = jiffies + (HZ * 5);
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u32 scontrol, sstatus;
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int rc;
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if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
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return rc;
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scontrol = scr_read(ap, SCR_CONTROL);
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scontrol = (scontrol & 0x0f0) | 0x300;
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scr_write_flush(ap, SCR_CONTROL, scontrol);
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if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
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return rc;
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/* Wait for phy to become ready, if necessary. */
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do {
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msleep(200);
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sstatus = scr_read(ap, SCR_STATUS);
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if ((rc = sata_scr_read(ap, SCR_STATUS, &sstatus)))
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return rc;
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if ((sstatus & 0xf) != 1)
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return 0;
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} while (time_before(jiffies, timeout));
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return -1;
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return -EBUSY;
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}
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/**
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@ -2367,21 +2373,20 @@ static int sata_phy_resume(struct ata_port *ap)
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*/
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void ata_std_probeinit(struct ata_port *ap)
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{
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if ((ap->flags & ATA_FLAG_SATA) && ap->ops->scr_read) {
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u32 spd;
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u32 scontrol;
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/* resume link */
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sata_phy_resume(ap);
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/* resume link */
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sata_phy_resume(ap);
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/* init sata_spd_limit to the current value */
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spd = (scr_read(ap, SCR_CONTROL) & 0xf0) >> 4;
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if (spd)
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ap->sata_spd_limit &= (1 << spd) - 1;
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/* wait for device */
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if (sata_dev_present(ap))
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ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
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/* init sata_spd_limit to the current value */
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if (sata_scr_read(ap, SCR_CONTROL, &scontrol) == 0) {
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int spd = (scontrol >> 4) & 0xf;
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ap->sata_spd_limit &= (1 << spd) - 1;
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}
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/* wait for device */
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if (ata_port_online(ap))
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ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
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}
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/**
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@ -2406,7 +2411,7 @@ int ata_std_softreset(struct ata_port *ap, unsigned int *classes)
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DPRINTK("ENTER\n");
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if (ap->ops->scr_read && !sata_dev_present(ap)) {
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if (ata_port_offline(ap)) {
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classes[0] = ATA_DEV_NONE;
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goto out;
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}
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@ -2457,6 +2462,7 @@ int ata_std_softreset(struct ata_port *ap, unsigned int *classes)
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int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
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{
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u32 scontrol;
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int rc;
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DPRINTK("ENTER\n");
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@ -2466,17 +2472,25 @@ int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
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* reconfiguration. This works for at least ICH7 AHCI
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* and Sil3124.
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*/
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scontrol = scr_read(ap, SCR_CONTROL);
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if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
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return rc;
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scontrol = (scontrol & 0x0f0) | 0x302;
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scr_write_flush(ap, SCR_CONTROL, scontrol);
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if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
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return rc;
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sata_set_spd(ap);
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}
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/* issue phy wake/reset */
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scontrol = scr_read(ap, SCR_CONTROL);
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if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
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return rc;
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scontrol = (scontrol & 0x0f0) | 0x301;
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scr_write_flush(ap, SCR_CONTROL, scontrol);
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if ((rc = sata_scr_write_flush(ap, SCR_CONTROL, scontrol)))
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return rc;
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/* Couldn't find anything in SATA I/II specs, but AHCI-1.1
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* 10.4.2 says at least 1 ms.
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@ -2487,7 +2501,7 @@ int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
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sata_phy_resume(ap);
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/* TODO: phy layer with polling, timeouts, etc. */
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if (!sata_dev_present(ap)) {
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if (ata_port_offline(ap)) {
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*class = ATA_DEV_NONE;
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DPRINTK("EXIT, link offline\n");
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return 0;
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@ -2527,8 +2541,7 @@ void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
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DPRINTK("ENTER\n");
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/* print link status */
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if (ap->cbl == ATA_CBL_SATA)
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sata_print_link_status(ap);
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sata_print_link_status(ap);
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/* re-enable interrupts */
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if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
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@ -2575,7 +2588,7 @@ int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
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ata_reset_fn_t hardreset;
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hardreset = NULL;
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if (ap->cbl == ATA_CBL_SATA && ap->ops->scr_read)
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if (sata_scr_valid(ap))
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hardreset = sata_std_hardreset;
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return ata_drive_probe_reset(ap, ata_std_probeinit,
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@ -1309,8 +1309,8 @@ static void mv_err_intr(struct ata_port *ap)
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edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
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if (EDMA_ERR_SERR & edma_err_cause) {
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serr = scr_read(ap, SCR_ERROR);
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scr_write_flush(ap, SCR_ERROR, serr);
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sata_scr_read(ap, SCR_ERROR, &serr);
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sata_scr_write_flush(ap, SCR_ERROR, serr);
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}
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if (EDMA_ERR_SELF_DIS & edma_err_cause) {
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struct mv_port_priv *pp = ap->private_data;
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@ -1934,15 +1934,16 @@ static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
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/* Issue COMRESET via SControl */
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comreset_retry:
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scr_write_flush(ap, SCR_CONTROL, 0x301);
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sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
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__msleep(1, can_sleep);
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scr_write_flush(ap, SCR_CONTROL, 0x300);
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sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
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__msleep(20, can_sleep);
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timeout = jiffies + msecs_to_jiffies(200);
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do {
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sstatus = scr_read(ap, SCR_STATUS) & 0x3;
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sata_scr_read(ap, SCR_STATUS, &sstatus);
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sstatus &= 0x3;
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if ((sstatus == 3) || (sstatus == 0))
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break;
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@ -1959,11 +1960,12 @@ comreset_retry:
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"SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
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mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
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if (sata_dev_present(ap)) {
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if (ata_port_online(ap)) {
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ata_port_probe(ap);
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} else {
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sata_scr_read(ap, SCR_STATUS, &sstatus);
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printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
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ap->id, scr_read(ap, SCR_STATUS));
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ap->id, sstatus);
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ata_port_disable(ap);
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return;
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}
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@ -464,7 +464,7 @@ static int sil24_softreset(struct ata_port *ap, unsigned int *class)
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DPRINTK("ENTER\n");
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if (!sata_dev_present(ap)) {
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if (ata_port_offline(ap)) {
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DPRINTK("PHY reports no device\n");
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*class = ATA_DEV_NONE;
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goto out;
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@ -531,7 +531,7 @@ static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
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sata_set_spd(ap);
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tout_msec = 100;
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if (sata_dev_present(ap))
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if (ata_port_online(ap))
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tout_msec = 5000;
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writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
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@ -544,7 +544,7 @@ static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
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msleep(100);
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if (tmp & PORT_CS_DEV_RST) {
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if (!sata_dev_present(ap))
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if (ata_port_offline(ap))
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return 0;
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reason = "link not ready";
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goto err;
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