forked from Minki/linux
i.MX27: Add ADS platform support
This patch adds basic support for the Freescale MX27ADS reference board. Currently only a serial console can be used. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
This commit is contained in:
Juergen Beisert
Robert Schwebel
parent
c46f585651
commit
80eedae6f0
826
arch/arm/configs/imx27ads_defconfig
Normal file
826
arch/arm/configs/imx27ads_defconfig
Normal file
@ -0,0 +1,826 @@
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#
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# Automatically generated make config: don't edit
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# Linux kernel version: 2.6.26-rc6
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# Fri Jun 20 16:29:34 2008
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#
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CONFIG_ARM=y
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_GENERIC_GPIO=y
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CONFIG_GENERIC_TIME=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_MMU=y
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# CONFIG_NO_IOPORT is not set
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CONFIG_GENERIC_HARDIRQS=y
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CONFIG_STACKTRACE_SUPPORT=y
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CONFIG_LOCKDEP_SUPPORT=y
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CONFIG_TRACE_IRQFLAGS_SUPPORT=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_GENERIC_IRQ_PROBE=y
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CONFIG_RWSEM_GENERIC_SPINLOCK=y
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_GENERIC_HWEIGHT=y
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CONFIG_GENERIC_CALIBRATE_DELAY=y
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CONFIG_ARCH_SUPPORTS_AOUT=y
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CONFIG_ZONE_DMA=y
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CONFIG_ARCH_MTD_XIP=y
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CONFIG_VECTORS_BASE=0xffff0000
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CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
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#
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# General setup
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#
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CONFIG_EXPERIMENTAL=y
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CONFIG_BROKEN_ON_SMP=y
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CONFIG_LOCK_KERNEL=y
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CONFIG_INIT_ENV_ARG_LIMIT=32
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CONFIG_LOCALVERSION=""
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CONFIG_LOCALVERSION_AUTO=y
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# CONFIG_SWAP is not set
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CONFIG_SYSVIPC=y
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CONFIG_SYSVIPC_SYSCTL=y
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CONFIG_POSIX_MQUEUE=y
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# CONFIG_BSD_PROCESS_ACCT is not set
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# CONFIG_TASKSTATS is not set
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# CONFIG_AUDIT is not set
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# CONFIG_IKCONFIG is not set
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CONFIG_LOG_BUF_SHIFT=14
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# CONFIG_CGROUPS is not set
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# CONFIG_GROUP_SCHED is not set
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CONFIG_SYSFS_DEPRECATED=y
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CONFIG_SYSFS_DEPRECATED_V2=y
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# CONFIG_RELAY is not set
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# CONFIG_NAMESPACES is not set
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# CONFIG_BLK_DEV_INITRD is not set
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# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
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CONFIG_SYSCTL=y
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CONFIG_EMBEDDED=y
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CONFIG_UID16=y
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CONFIG_SYSCTL_SYSCALL=y
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CONFIG_SYSCTL_SYSCALL_CHECK=y
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CONFIG_KALLSYMS=y
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CONFIG_KALLSYMS_EXTRA_PASS=y
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CONFIG_HOTPLUG=y
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CONFIG_PRINTK=y
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CONFIG_BUG=y
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CONFIG_ELF_CORE=y
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CONFIG_COMPAT_BRK=y
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CONFIG_BASE_FULL=y
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CONFIG_FUTEX=y
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CONFIG_ANON_INODES=y
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CONFIG_EPOLL=y
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CONFIG_SIGNALFD=y
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CONFIG_TIMERFD=y
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CONFIG_EVENTFD=y
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CONFIG_SHMEM=y
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CONFIG_VM_EVENT_COUNTERS=y
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CONFIG_SLAB=y
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# CONFIG_SLUB is not set
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# CONFIG_SLOB is not set
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# CONFIG_PROFILING is not set
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# CONFIG_MARKERS is not set
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CONFIG_HAVE_OPROFILE=y
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# CONFIG_KPROBES is not set
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CONFIG_HAVE_KPROBES=y
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CONFIG_HAVE_KRETPROBES=y
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# CONFIG_HAVE_DMA_ATTRS is not set
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CONFIG_PROC_PAGE_MONITOR=y
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CONFIG_SLABINFO=y
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CONFIG_RT_MUTEXES=y
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# CONFIG_TINY_SHMEM is not set
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CONFIG_BASE_SMALL=0
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CONFIG_MODULES=y
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# CONFIG_MODULE_FORCE_LOAD is not set
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_MODULE_FORCE_UNLOAD is not set
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# CONFIG_MODVERSIONS is not set
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# CONFIG_MODULE_SRCVERSION_ALL is not set
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# CONFIG_KMOD is not set
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CONFIG_BLOCK=y
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# CONFIG_LBD is not set
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# CONFIG_BLK_DEV_IO_TRACE is not set
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# CONFIG_LSF is not set
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# CONFIG_BLK_DEV_BSG is not set
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#
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# IO Schedulers
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#
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CONFIG_IOSCHED_NOOP=y
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# CONFIG_IOSCHED_AS is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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# CONFIG_DEFAULT_AS is not set
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# CONFIG_DEFAULT_DEADLINE is not set
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# CONFIG_DEFAULT_CFQ is not set
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CONFIG_DEFAULT_NOOP=y
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CONFIG_DEFAULT_IOSCHED="noop"
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CONFIG_CLASSIC_RCU=y
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#
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# System Type
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#
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# CONFIG_ARCH_AAEC2000 is not set
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# CONFIG_ARCH_INTEGRATOR is not set
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# CONFIG_ARCH_REALVIEW is not set
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# CONFIG_ARCH_VERSATILE is not set
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# CONFIG_ARCH_AT91 is not set
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# CONFIG_ARCH_CLPS7500 is not set
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# CONFIG_ARCH_CLPS711X is not set
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# CONFIG_ARCH_CO285 is not set
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# CONFIG_ARCH_EBSA110 is not set
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# CONFIG_ARCH_EP93XX is not set
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# CONFIG_ARCH_FOOTBRIDGE is not set
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# CONFIG_ARCH_NETX is not set
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# CONFIG_ARCH_H720X is not set
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# CONFIG_ARCH_IMX is not set
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# CONFIG_ARCH_IOP13XX is not set
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# CONFIG_ARCH_IOP32X is not set
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# CONFIG_ARCH_IOP33X is not set
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# CONFIG_ARCH_IXP23XX is not set
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# CONFIG_ARCH_IXP2000 is not set
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# CONFIG_ARCH_IXP4XX is not set
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# CONFIG_ARCH_L7200 is not set
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# CONFIG_ARCH_KS8695 is not set
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# CONFIG_ARCH_NS9XXX is not set
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CONFIG_ARCH_MXC=y
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# CONFIG_ARCH_ORION5X is not set
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# CONFIG_ARCH_PNX4008 is not set
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# CONFIG_ARCH_PXA is not set
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# CONFIG_ARCH_RPC is not set
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# CONFIG_ARCH_SA1100 is not set
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# CONFIG_ARCH_S3C2410 is not set
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# CONFIG_ARCH_SHARK is not set
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# CONFIG_ARCH_LH7A40X is not set
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# CONFIG_ARCH_DAVINCI is not set
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# CONFIG_ARCH_OMAP is not set
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# CONFIG_ARCH_MSM7X00A is not set
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#
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# Boot options
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#
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#
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# Power management
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#
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#
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# Freescale MXC Implementations
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#
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CONFIG_ARCH_MX2=y
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# CONFIG_ARCH_MX3 is not set
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#
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# MX2 family CPU support
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#
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CONFIG_MACH_MX27=y
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#
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# MX2 Platforms
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#
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CONFIG_MACH_MX27ADS=y
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# CONFIG_MACH_PCM038 is not set
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#
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# Processor Type
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#
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CONFIG_CPU_32=y
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CONFIG_CPU_ARM926T=y
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CONFIG_CPU_32v5=y
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CONFIG_CPU_ABRT_EV5TJ=y
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CONFIG_CPU_PABRT_NOIFAR=y
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CONFIG_CPU_CACHE_VIVT=y
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CONFIG_CPU_COPY_V4WB=y
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CONFIG_CPU_TLB_V4WBI=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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#
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# Processor Features
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#
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CONFIG_ARM_THUMB=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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# CONFIG_CPU_DCACHE_DISABLE is not set
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# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
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# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
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# CONFIG_OUTER_CACHE is not set
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#
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# Bus support
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#
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# CONFIG_PCI_SYSCALL is not set
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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# CONFIG_PCCARD is not set
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#
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# Kernel Features
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#
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CONFIG_TICK_ONESHOT=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_PREEMPT=y
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CONFIG_HZ=100
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CONFIG_AEABI=y
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# CONFIG_OABI_COMPAT is not set
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# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
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CONFIG_SELECT_MEMORY_MODEL=y
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CONFIG_FLATMEM_MANUAL=y
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# CONFIG_DISCONTIGMEM_MANUAL is not set
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# CONFIG_SPARSEMEM_MANUAL is not set
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CONFIG_FLATMEM=y
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CONFIG_FLAT_NODE_MEM_MAP=y
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# CONFIG_SPARSEMEM_STATIC is not set
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# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_SPLIT_PTLOCK_CPUS=4096
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# CONFIG_RESOURCES_64BIT is not set
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CONFIG_ZONE_DMA_FLAG=1
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CONFIG_BOUNCE=y
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CONFIG_VIRT_TO_BUS=y
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CONFIG_ALIGNMENT_TRAP=y
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#
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# Boot options
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#
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE=""
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# CONFIG_XIP_KERNEL is not set
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# CONFIG_KEXEC is not set
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#
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# Floating point emulation
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#
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#
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# At least one emulation must be selected
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#
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# CONFIG_VFP is not set
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#
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# Userspace binary formats
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#
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CONFIG_BINFMT_ELF=y
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# CONFIG_BINFMT_AOUT is not set
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# CONFIG_BINFMT_MISC is not set
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#
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# Power management options
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#
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# CONFIG_PM is not set
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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#
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# Networking
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#
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CONFIG_NET=y
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#
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# Networking options
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#
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CONFIG_PACKET=y
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CONFIG_PACKET_MMAP=y
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CONFIG_UNIX=y
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# CONFIG_NET_KEY is not set
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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# CONFIG_IP_ADVANCED_ROUTER is not set
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CONFIG_IP_FIB_HASH=y
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CONFIG_IP_PNP=y
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# CONFIG_IP_PNP_DHCP is not set
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# CONFIG_IP_PNP_BOOTP is not set
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# CONFIG_IP_PNP_RARP is not set
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# CONFIG_NET_IPIP is not set
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# CONFIG_NET_IPGRE is not set
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# CONFIG_IP_MROUTE is not set
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# CONFIG_ARPD is not set
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# CONFIG_SYN_COOKIES is not set
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# CONFIG_INET_AH is not set
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# CONFIG_INET_ESP is not set
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# CONFIG_INET_IPCOMP is not set
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# CONFIG_INET_XFRM_TUNNEL is not set
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# CONFIG_INET_TUNNEL is not set
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# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
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# CONFIG_INET_XFRM_MODE_TUNNEL is not set
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# CONFIG_INET_XFRM_MODE_BEET is not set
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# CONFIG_INET_LRO is not set
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# CONFIG_INET_DIAG is not set
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# CONFIG_TCP_CONG_ADVANCED is not set
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CONFIG_TCP_CONG_CUBIC=y
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CONFIG_DEFAULT_TCP_CONG="cubic"
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# CONFIG_TCP_MD5SIG is not set
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# CONFIG_IPV6 is not set
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# CONFIG_NETWORK_SECMARK is not set
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# CONFIG_NETFILTER is not set
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# CONFIG_IP_DCCP is not set
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# CONFIG_IP_SCTP is not set
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# CONFIG_TIPC is not set
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# CONFIG_ATM is not set
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# CONFIG_BRIDGE is not set
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# CONFIG_VLAN_8021Q is not set
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# CONFIG_DECNET is not set
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# CONFIG_LLC2 is not set
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# CONFIG_IPX is not set
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# CONFIG_ATALK is not set
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# CONFIG_X25 is not set
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# CONFIG_LAPB is not set
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# CONFIG_ECONET is not set
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# CONFIG_WAN_ROUTER is not set
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# CONFIG_NET_SCHED is not set
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#
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# Network testing
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#
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# CONFIG_NET_PKTGEN is not set
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# CONFIG_HAMRADIO is not set
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# CONFIG_CAN is not set
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||||
# CONFIG_IRDA is not set
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||||
# CONFIG_BT is not set
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||||
# CONFIG_AF_RXRPC is not set
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||||
|
||||
#
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||||
# Wireless
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||||
#
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||||
# CONFIG_CFG80211 is not set
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||||
# CONFIG_WIRELESS_EXT is not set
|
||||
# CONFIG_MAC80211 is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
# CONFIG_RFKILL is not set
|
||||
# CONFIG_NET_9P is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
# CONFIG_CONNECTOR is not set
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_DEBUG is not set
|
||||
# CONFIG_MTD_CONCAT is not set
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_AFS_PARTS is not set
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# User Modules And Translation Layers
|
||||
#
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLKDEVS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
# CONFIG_FTL is not set
|
||||
# CONFIG_NFTL is not set
|
||||
# CONFIG_INFTL is not set
|
||||
# CONFIG_RFD_FTL is not set
|
||||
# CONFIG_SSFDC is not set
|
||||
# CONFIG_MTD_OOPS is not set
|
||||
|
||||
#
|
||||
# RAM/ROM/Flash chip drivers
|
||||
#
|
||||
CONFIG_MTD_CFI=y
|
||||
# CONFIG_MTD_JEDECPROBE is not set
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_NOSWAP=y
|
||||
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
|
||||
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
|
||||
CONFIG_MTD_CFI_GEOMETRY=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
# CONFIG_MTD_CFI_I2 is not set
|
||||
# CONFIG_MTD_CFI_I4 is not set
|
||||
# CONFIG_MTD_CFI_I8 is not set
|
||||
# CONFIG_MTD_OTP is not set
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
# CONFIG_MTD_CFI_AMDSTD is not set
|
||||
# CONFIG_MTD_CFI_STAA is not set
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
# CONFIG_MTD_RAM is not set
|
||||
# CONFIG_MTD_ROM is not set
|
||||
# CONFIG_MTD_ABSENT is not set
|
||||
# CONFIG_MTD_XIP is not set
|
||||
|
||||
#
|
||||
# Mapping drivers for chip access
|
||||
#
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_START=0x00000000
|
||||
CONFIG_MTD_PHYSMAP_LEN=0x0
|
||||
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
|
||||
# CONFIG_MTD_ARM_INTEGRATOR is not set
|
||||
# CONFIG_MTD_PLATRAM is not set
|
||||
|
||||
#
|
||||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
# CONFIG_MTD_PHRAM is not set
|
||||
# CONFIG_MTD_MTDRAM is not set
|
||||
# CONFIG_MTD_BLOCK2MTD is not set
|
||||
|
||||
#
|
||||
# Disk-On-Chip Device Drivers
|
||||
#
|
||||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
# CONFIG_MTD_UBI is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
# CONFIG_BLK_DEV_LOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_DMA is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
# CONFIG_ATA is not set
|
||||
# CONFIG_MD is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NETDEVICES_MULTIQUEUE is not set
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_MACVLAN is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
# CONFIG_TUN is not set
|
||||
# CONFIG_VETH is not set
|
||||
# CONFIG_PHYLIB is not set
|
||||
CONFIG_NET_ETHERNET=y
|
||||
# CONFIG_MII is not set
|
||||
# CONFIG_AX88796 is not set
|
||||
# CONFIG_SMC91X is not set
|
||||
# CONFIG_DM9000 is not set
|
||||
# CONFIG_IBM_NEW_EMAC_ZMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_RGMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_TAH is not set
|
||||
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_FEC_OLD is not set
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
|
||||
#
|
||||
# Wireless LAN
|
||||
#
|
||||
# CONFIG_WLAN_PRE80211 is not set
|
||||
# CONFIG_WLAN_80211 is not set
|
||||
# CONFIG_IWLWIFI_LEDS is not set
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
# CONFIG_ISDN is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
# CONFIG_INPUT_POLLDEV is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
# CONFIG_TOUCHSCREEN_FUJITSU is not set
|
||||
# CONFIG_TOUCHSCREEN_GUNZE is not set
|
||||
# CONFIG_TOUCHSCREEN_ELO is not set
|
||||
# CONFIG_TOUCHSCREEN_MTOUCH is not set
|
||||
# CONFIG_TOUCHSCREEN_MK712 is not set
|
||||
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
|
||||
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
|
||||
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
|
||||
# CONFIG_TOUCHSCREEN_UCB1400 is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_DEVKMEM=y
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
# CONFIG_SERIAL_8250 is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
# CONFIG_SERIAL_IMX is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_NVRAM is not set
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_I2C is not set
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_HAVE_GPIO_LIB=y
|
||||
|
||||
#
|
||||
# GPIO Support
|
||||
#
|
||||
|
||||
#
|
||||
# I2C GPIO expanders:
|
||||
#
|
||||
|
||||
#
|
||||
# SPI GPIO expanders:
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
# CONFIG_POWER_SUPPLY is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_WATCHDOG is not set
|
||||
|
||||
#
|
||||
# Sonics Silicon Backplane
|
||||
#
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
# CONFIG_SSB is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_MFD_ASIC3 is not set
|
||||
# CONFIG_HTC_EGPIO is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia core support
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
# CONFIG_DVB_CORE is not set
|
||||
# CONFIG_VIDEO_MEDIA is not set
|
||||
|
||||
#
|
||||
# Multimedia drivers
|
||||
#
|
||||
# CONFIG_DAB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_VGASTATE is not set
|
||||
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
|
||||
# CONFIG_FB is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Display device support
|
||||
#
|
||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
# CONFIG_UIO is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_EXT4DEV_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY is not set
|
||||
# CONFIG_QUOTA is not set
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_TMPFS_POSIX_ACL is not set
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_DEBUG=0
|
||||
CONFIG_JFFS2_FS_WRITEBUFFER=y
|
||||
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
|
||||
# CONFIG_JFFS2_SUMMARY is not set
|
||||
# CONFIG_JFFS2_FS_XATTR is not set
|
||||
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
# CONFIG_JFFS2_LZO is not set
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
# CONFIG_JFFS2_RUBIN is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
# CONFIG_NFS_V4 is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_SUNRPC_BIND34 is not set
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_DEFAULT="iso8859-1"
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
# CONFIG_NLS_CODEPAGE_737 is not set
|
||||
# CONFIG_NLS_CODEPAGE_775 is not set
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
# CONFIG_NLS_CODEPAGE_852 is not set
|
||||
# CONFIG_NLS_CODEPAGE_855 is not set
|
||||
# CONFIG_NLS_CODEPAGE_857 is not set
|
||||
# CONFIG_NLS_CODEPAGE_860 is not set
|
||||
# CONFIG_NLS_CODEPAGE_861 is not set
|
||||
# CONFIG_NLS_CODEPAGE_862 is not set
|
||||
# CONFIG_NLS_CODEPAGE_863 is not set
|
||||
# CONFIG_NLS_CODEPAGE_864 is not set
|
||||
# CONFIG_NLS_CODEPAGE_865 is not set
|
||||
# CONFIG_NLS_CODEPAGE_866 is not set
|
||||
# CONFIG_NLS_CODEPAGE_869 is not set
|
||||
# CONFIG_NLS_CODEPAGE_936 is not set
|
||||
# CONFIG_NLS_CODEPAGE_950 is not set
|
||||
# CONFIG_NLS_CODEPAGE_932 is not set
|
||||
# CONFIG_NLS_CODEPAGE_949 is not set
|
||||
# CONFIG_NLS_CODEPAGE_874 is not set
|
||||
# CONFIG_NLS_ISO8859_8 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1250 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1251 is not set
|
||||
# CONFIG_NLS_ASCII is not set
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
# CONFIG_NLS_ISO8859_2 is not set
|
||||
# CONFIG_NLS_ISO8859_3 is not set
|
||||
# CONFIG_NLS_ISO8859_4 is not set
|
||||
# CONFIG_NLS_ISO8859_5 is not set
|
||||
# CONFIG_NLS_ISO8859_6 is not set
|
||||
# CONFIG_NLS_ISO8859_7 is not set
|
||||
# CONFIG_NLS_ISO8859_9 is not set
|
||||
# CONFIG_NLS_ISO8859_13 is not set
|
||||
# CONFIG_NLS_ISO8859_14 is not set
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
# CONFIG_NLS_KOI8_R is not set
|
||||
# CONFIG_NLS_KOI8_U is not set
|
||||
# CONFIG_NLS_UTF8 is not set
|
||||
# CONFIG_DLM is not set
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
CONFIG_ENABLE_WARN_DEPRECATED=y
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
# CONFIG_SAMPLES is not set
|
||||
# CONFIG_DEBUG_USER is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
|
||||
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_CRC7 is not set
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_PLIST=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_DMA=y
|
||||
@ -9,3 +9,10 @@ config MACH_MX27
|
||||
|
||||
comment "MX2 Platforms"
|
||||
depends on ARCH_MX2
|
||||
|
||||
config MACH_MX27ADS
|
||||
bool "MX27ADS platform"
|
||||
depends on MACH_MX27
|
||||
help
|
||||
Include support for MX27ADS platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
@ -8,3 +8,5 @@ obj-y := system.o generic.o devices.o serial.o
|
||||
|
||||
obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
|
||||
obj-$(CONFIG_MACH_MX27) += clock_imx27.o
|
||||
|
||||
obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o
|
||||
|
||||
304
arch/arm/mach-mx2/mx27ads.c
Normal file
304
arch/arm/mach-mx2/mx27ads.c
Normal file
@ -0,0 +1,304 @@
|
||||
/*
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
|
||||
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/map.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <asm/arch/common.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/imx-uart.h>
|
||||
#include <asm/arch/iomux-mx1-mx2.h>
|
||||
#include <asm/arch/board-mx27ads.h>
|
||||
|
||||
/* ADS's NOR flash */
|
||||
static struct physmap_flash_data mx27ads_flash_data = {
|
||||
.width = 2,
|
||||
};
|
||||
|
||||
static struct resource mx27ads_flash_resource = {
|
||||
.start = 0xc0000000,
|
||||
.end = 0xc0000000 + 0x02000000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
||||
};
|
||||
|
||||
static struct platform_device mx27ads_nor_mtd_device = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mx27ads_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &mx27ads_flash_resource,
|
||||
};
|
||||
|
||||
static int mxc_uart0_pins[] = {
|
||||
PE12_PF_UART1_TXD,
|
||||
PE13_PF_UART1_RXD,
|
||||
PE14_PF_UART1_CTS,
|
||||
PE15_PF_UART1_RTS
|
||||
};
|
||||
|
||||
static int uart_mxc_port0_init(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
|
||||
ARRAY_SIZE(mxc_uart0_pins),
|
||||
MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
|
||||
}
|
||||
|
||||
static int uart_mxc_port0_exit(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
|
||||
ARRAY_SIZE(mxc_uart0_pins),
|
||||
MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
|
||||
}
|
||||
|
||||
static int mxc_uart1_pins[] = {
|
||||
PE3_PF_UART2_CTS,
|
||||
PE4_PF_UART2_RTS,
|
||||
PE6_PF_UART2_TXD,
|
||||
PE7_PF_UART2_RXD
|
||||
};
|
||||
|
||||
static int uart_mxc_port1_init(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
|
||||
ARRAY_SIZE(mxc_uart1_pins),
|
||||
MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
|
||||
}
|
||||
|
||||
static int uart_mxc_port1_exit(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
|
||||
ARRAY_SIZE(mxc_uart1_pins),
|
||||
MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
|
||||
}
|
||||
|
||||
static int mxc_uart2_pins[] = {
|
||||
PE8_PF_UART3_TXD,
|
||||
PE9_PF_UART3_RXD,
|
||||
PE10_PF_UART3_CTS,
|
||||
PE11_PF_UART3_RTS
|
||||
};
|
||||
|
||||
static int uart_mxc_port2_init(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
|
||||
ARRAY_SIZE(mxc_uart2_pins),
|
||||
MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
|
||||
}
|
||||
|
||||
static int uart_mxc_port2_exit(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
|
||||
ARRAY_SIZE(mxc_uart2_pins),
|
||||
MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
|
||||
}
|
||||
|
||||
static int mxc_uart3_pins[] = {
|
||||
PB26_AF_UART4_RTS,
|
||||
PB28_AF_UART4_TXD,
|
||||
PB29_AF_UART4_CTS,
|
||||
PB31_AF_UART4_RXD
|
||||
};
|
||||
|
||||
static int uart_mxc_port3_init(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
|
||||
ARRAY_SIZE(mxc_uart3_pins),
|
||||
MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
|
||||
}
|
||||
|
||||
static int uart_mxc_port3_exit(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
|
||||
ARRAY_SIZE(mxc_uart3_pins),
|
||||
MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
|
||||
}
|
||||
|
||||
static int mxc_uart4_pins[] = {
|
||||
PB18_AF_UART5_TXD,
|
||||
PB19_AF_UART5_RXD,
|
||||
PB20_AF_UART5_CTS,
|
||||
PB21_AF_UART5_RTS
|
||||
};
|
||||
|
||||
static int uart_mxc_port4_init(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
|
||||
ARRAY_SIZE(mxc_uart4_pins),
|
||||
MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
|
||||
}
|
||||
|
||||
static int uart_mxc_port4_exit(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
|
||||
ARRAY_SIZE(mxc_uart4_pins),
|
||||
MXC_GPIO_ALLOC_MODE_RELEASE, "UART4");
|
||||
}
|
||||
|
||||
static int mxc_uart5_pins[] = {
|
||||
PB10_AF_UART6_TXD,
|
||||
PB12_AF_UART6_CTS,
|
||||
PB11_AF_UART6_RXD,
|
||||
PB13_AF_UART6_RTS
|
||||
};
|
||||
|
||||
static int uart_mxc_port5_init(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
|
||||
ARRAY_SIZE(mxc_uart5_pins),
|
||||
MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
|
||||
}
|
||||
|
||||
static int uart_mxc_port5_exit(struct platform_device *pdev)
|
||||
{
|
||||
return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
|
||||
ARRAY_SIZE(mxc_uart5_pins),
|
||||
MXC_GPIO_ALLOC_MODE_RELEASE, "UART5");
|
||||
}
|
||||
|
||||
static struct platform_device *platform_devices[] __initdata = {
|
||||
&mx27ads_nor_mtd_device,
|
||||
};
|
||||
|
||||
static int mxc_fec_pins[] = {
|
||||
PD0_AIN_FEC_TXD0,
|
||||
PD1_AIN_FEC_TXD1,
|
||||
PD2_AIN_FEC_TXD2,
|
||||
PD3_AIN_FEC_TXD3,
|
||||
PD4_AOUT_FEC_RX_ER,
|
||||
PD5_AOUT_FEC_RXD1,
|
||||
PD6_AOUT_FEC_RXD2,
|
||||
PD7_AOUT_FEC_RXD3,
|
||||
PD8_AF_FEC_MDIO,
|
||||
PD9_AIN_FEC_MDC,
|
||||
PD10_AOUT_FEC_CRS,
|
||||
PD11_AOUT_FEC_TX_CLK,
|
||||
PD12_AOUT_FEC_RXD0,
|
||||
PD13_AOUT_FEC_RX_DV,
|
||||
PD14_AOUT_FEC_CLR,
|
||||
PD15_AOUT_FEC_COL,
|
||||
PD16_AIN_FEC_TX_ER,
|
||||
PF23_AIN_FEC_TX_EN
|
||||
};
|
||||
|
||||
static void gpio_fec_active(void)
|
||||
{
|
||||
mxc_gpio_setup_multiple_pins(mxc_fec_pins,
|
||||
ARRAY_SIZE(mxc_fec_pins),
|
||||
MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
|
||||
}
|
||||
|
||||
static void gpio_fec_inactive(void)
|
||||
{
|
||||
mxc_gpio_setup_multiple_pins(mxc_fec_pins,
|
||||
ARRAY_SIZE(mxc_fec_pins),
|
||||
MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
|
||||
}
|
||||
|
||||
static struct imxuart_platform_data uart_pdata[] = {
|
||||
{
|
||||
.init = uart_mxc_port0_init,
|
||||
.exit = uart_mxc_port0_exit,
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
}, {
|
||||
.init = uart_mxc_port1_init,
|
||||
.exit = uart_mxc_port1_exit,
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
}, {
|
||||
.init = uart_mxc_port2_init,
|
||||
.exit = uart_mxc_port2_exit,
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
}, {
|
||||
.init = uart_mxc_port3_init,
|
||||
.exit = uart_mxc_port3_exit,
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
}, {
|
||||
.init = uart_mxc_port4_init,
|
||||
.exit = uart_mxc_port4_exit,
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
}, {
|
||||
.init = uart_mxc_port5_init,
|
||||
.exit = uart_mxc_port5_exit,
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init mx27ads_board_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
gpio_fec_active();
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
imx_init_uart(i, &uart_pdata[i]);
|
||||
|
||||
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
|
||||
}
|
||||
|
||||
static void __init mx27ads_timer_init(void)
|
||||
{
|
||||
unsigned long fref = 26000000;
|
||||
|
||||
if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
|
||||
fref = 27000000;
|
||||
|
||||
mxc_clocks_init(fref);
|
||||
mxc_timer_init("gpt_clk.0");
|
||||
}
|
||||
|
||||
struct sys_timer mx27ads_timer = {
|
||||
.init = mx27ads_timer_init,
|
||||
};
|
||||
|
||||
static struct map_desc mx27ads_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = PBC_BASE_ADDRESS,
|
||||
.pfn = __phys_to_pfn(CS4_BASE_ADDR),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
void __init mx27ads_map_io(void)
|
||||
{
|
||||
mxc_map_io();
|
||||
iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
|
||||
}
|
||||
|
||||
MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
|
||||
/* maintainer: Freescale Semiconductor, Inc. */
|
||||
.phys_io = AIPI_BASE_ADDR,
|
||||
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
|
||||
.boot_params = PHYS_OFFSET + 0x100,
|
||||
.map_io = mx27ads_map_io,
|
||||
.init_irq = mxc_init_irq,
|
||||
.init_machine = mx27ads_board_init,
|
||||
.timer = &mx27ads_timer,
|
||||
MACHINE_END
|
||||
|
||||
354
include/asm-arm/arch-mxc/board-mx27ads.h
Normal file
354
include/asm-arm/arch-mxc/board-mx27ads.h
Normal file
@ -0,0 +1,354 @@
|
||||
/*
|
||||
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
|
||||
#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
|
||||
|
||||
/* external interrupt multiplexer */
|
||||
#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
|
||||
|
||||
#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
|
||||
#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
|
||||
#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
|
||||
#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
|
||||
|
||||
#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
|
||||
MXC_MAX_VIRTUAL_INTS)
|
||||
|
||||
/*
|
||||
* MXC UART EVB board level configurations
|
||||
*/
|
||||
|
||||
#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
|
||||
#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
|
||||
#define MXC_LL_EXTUART_16BIT_BUS
|
||||
|
||||
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
|
||||
#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
|
||||
|
||||
/*
|
||||
* @name Memory Size parameters
|
||||
*/
|
||||
|
||||
/*
|
||||
* Size of SDRAM memory
|
||||
*/
|
||||
#define SDRAM_MEM_SIZE SZ_128M
|
||||
|
||||
/*
|
||||
* PBC Controller parameters
|
||||
*/
|
||||
|
||||
/*
|
||||
* Base address of PBC controller, CS4
|
||||
*/
|
||||
#define PBC_BASE_ADDRESS 0xEB000000
|
||||
#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
|
||||
|
||||
/*
|
||||
* PBC Interupt name definitions
|
||||
*/
|
||||
#define PBC_GPIO1_0 0
|
||||
#define PBC_GPIO1_1 1
|
||||
#define PBC_GPIO1_2 2
|
||||
#define PBC_GPIO1_3 3
|
||||
#define PBC_GPIO1_4 4
|
||||
#define PBC_GPIO1_5 5
|
||||
|
||||
#define PBC_INTR_MAX_NUM 6
|
||||
#define PBC_INTR_SHARED_MAX_NUM 8
|
||||
|
||||
/* When the PBC address connection is fixed in h/w, defined as 1 */
|
||||
#define PBC_ADDR_SH 0
|
||||
|
||||
/* Offsets for the PBC Controller register */
|
||||
/*
|
||||
* PBC Board version register offset
|
||||
*/
|
||||
#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 1 set address.
|
||||
*/
|
||||
#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 1 clear address.
|
||||
*/
|
||||
#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 2 set address.
|
||||
*/
|
||||
#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 2 clear address.
|
||||
*/
|
||||
#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 3 set address.
|
||||
*/
|
||||
#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 3 clear address.
|
||||
*/
|
||||
#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 3 set address.
|
||||
*/
|
||||
#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board control register 4 clear address.
|
||||
*/
|
||||
#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
|
||||
/*PBC_ADDR_SH
|
||||
* PBC Board status register 1.
|
||||
*/
|
||||
#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board interrupt status register.
|
||||
*/
|
||||
#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Board interrupt current status register.
|
||||
*/
|
||||
#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Interrupt mask register set address.
|
||||
*/
|
||||
#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* PBC Interrupt mask register clear address.
|
||||
*/
|
||||
#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
|
||||
/*
|
||||
* External UART A.
|
||||
*/
|
||||
#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* UART 4 Expanding Signal Status.
|
||||
*/
|
||||
#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* UART 4 Expanding Signal Control Set.
|
||||
*/
|
||||
#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* UART 4 Expanding Signal Control Clear.
|
||||
*/
|
||||
#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* Ethernet Controller IO base address.
|
||||
*/
|
||||
#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* Ethernet Controller Memory base address.
|
||||
*/
|
||||
#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
|
||||
/*
|
||||
* Ethernet Controller DMA base address.
|
||||
*/
|
||||
#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
|
||||
|
||||
/* PBC Board Version Register bit definition */
|
||||
#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
|
||||
#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
|
||||
|
||||
/* PBC Board Control Register 1 bit definitions */
|
||||
#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
|
||||
#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
|
||||
#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
|
||||
#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
|
||||
#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
|
||||
|
||||
/* PBC Board Control Register 2 bit definitions */
|
||||
#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
|
||||
#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
|
||||
#define PBC_BCTRL2_ATAFEC_EN 0X0010
|
||||
#define PBC_BCTRL2_ATAFEC_SEL 0X0020
|
||||
#define PBC_BCTRL2_ATA_EN 0X0040
|
||||
#define PBC_BCTRL2_IRDA_SD 0X0080
|
||||
#define PBC_BCTRL2_IRDA_EN 0X0100
|
||||
#define PBC_BCTRL2_CCTL10 0X0200
|
||||
#define PBC_BCTRL2_CCTL11 0X0400
|
||||
|
||||
/* PBC Board Control Register 3 bit definitions */
|
||||
#define PBC_BCTRL3_HSH_EN 0X0020
|
||||
#define PBC_BCTRL3_FSH_MOD 0X0040
|
||||
#define PBC_BCTRL3_OTG_HS_EN 0X0080
|
||||
#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
|
||||
#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
|
||||
#define PBC_BCTRL3_USB_OTG_ON 0X0800
|
||||
#define PBC_BCTRL3_USB_FSH_ON 0X1000
|
||||
|
||||
/* PBC Board Control Register 4 bit definitions */
|
||||
#define PBC_BCTRL4_REGEN_SEL 0X0001
|
||||
#define PBC_BCTRL4_USER_OFF 0X0002
|
||||
#define PBC_BCTRL4_VIB_EN 0X0004
|
||||
#define PBC_BCTRL4_PWRGT1_EN 0X0008
|
||||
#define PBC_BCTRL4_PWRGT2_EN 0X0010
|
||||
#define PBC_BCTRL4_STDBY_PRI 0X0020
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*
|
||||
* Enumerations for SD cards and memory stick card. This corresponds to
|
||||
* the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
|
||||
*/
|
||||
enum mxc_card_no {
|
||||
MXC_CARD_SD2 = 0,
|
||||
MXC_CARD_SD3,
|
||||
MXC_CARD_MS,
|
||||
MXC_CARD_SD1,
|
||||
MXC_CARD_MIN = MXC_CARD_SD2,
|
||||
MXC_CARD_MAX = MXC_CARD_SD1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#define MXC_CPLD_VER_1_50 0x01
|
||||
|
||||
/*
|
||||
* PBC BSTAT Register bit definitions
|
||||
*/
|
||||
#define PBC_BSTAT_PRI_INT 0X0001
|
||||
#define PBC_BSTAT_USB_BYP 0X0002
|
||||
#define PBC_BSTAT_ATA_IOCS16 0X0004
|
||||
#define PBC_BSTAT_ATA_CBLID 0X0008
|
||||
#define PBC_BSTAT_ATA_DASP 0X0010
|
||||
#define PBC_BSTAT_PWR_RDY 0X0020
|
||||
#define PBC_BSTAT_SD3_WP 0X0100
|
||||
#define PBC_BSTAT_SD2_WP 0X0200
|
||||
#define PBC_BSTAT_SD1_WP 0X0400
|
||||
#define PBC_BSTAT_SD3_DET 0X0800
|
||||
#define PBC_BSTAT_SD2_DET 0X1000
|
||||
#define PBC_BSTAT_SD1_DET 0X2000
|
||||
#define PBC_BSTAT_MS_DET 0X4000
|
||||
#define PBC_BSTAT_SD3_DET_BIT 11
|
||||
#define PBC_BSTAT_SD2_DET_BIT 12
|
||||
#define PBC_BSTAT_SD1_DET_BIT 13
|
||||
#define PBC_BSTAT_MS_DET_BIT 14
|
||||
#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
|
||||
((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
|
||||
((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
|
||||
((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
|
||||
0x0))))
|
||||
|
||||
/*
|
||||
* PBC UART Control Register bit definitions
|
||||
*/
|
||||
#define PBC_UCTRL_DCE_DCD 0X0001
|
||||
#define PBC_UCTRL_DCE_DSR 0X0002
|
||||
#define PBC_UCTRL_DCE_RI 0X0004
|
||||
#define PBC_UCTRL_DTE_DTR 0X0100
|
||||
|
||||
/*
|
||||
* PBC UART Status Register bit definitions
|
||||
*/
|
||||
#define PBC_USTAT_DTE_DCD 0X0001
|
||||
#define PBC_USTAT_DTE_DSR 0X0002
|
||||
#define PBC_USTAT_DTE_RI 0X0004
|
||||
#define PBC_USTAT_DCE_DTR 0X0100
|
||||
|
||||
/*
|
||||
* PBC Interupt mask register bit definitions
|
||||
*/
|
||||
#define PBC_INTR_SD3_R_EN_BIT 4
|
||||
#define PBC_INTR_SD2_R_EN_BIT 0
|
||||
#define PBC_INTR_SD1_R_EN_BIT 6
|
||||
#define PBC_INTR_MS_R_EN_BIT 5
|
||||
#define PBC_INTR_SD3_EN_BIT 13
|
||||
#define PBC_INTR_SD2_EN_BIT 12
|
||||
#define PBC_INTR_MS_EN_BIT 14
|
||||
#define PBC_INTR_SD1_EN_BIT 15
|
||||
|
||||
#define PBC_INTR_SD2_R_EN 0x0001
|
||||
#define PBC_INTR_LOW_BAT 0X0002
|
||||
#define PBC_INTR_OTG_FSOVER 0X0004
|
||||
#define PBC_INTR_FSH_OVER 0X0008
|
||||
#define PBC_INTR_SD3_R_EN 0x0010
|
||||
#define PBC_INTR_MS_R_EN 0x0020
|
||||
#define PBC_INTR_SD1_R_EN 0x0040
|
||||
#define PBC_INTR_FEC_INT 0X0080
|
||||
#define PBC_INTR_ENET_INT 0X0100
|
||||
#define PBC_INTR_OTGFS_INT 0X0200
|
||||
#define PBC_INTR_XUART_INT 0X0400
|
||||
#define PBC_INTR_CCTL12 0X0800
|
||||
#define PBC_INTR_SD2_EN 0x1000
|
||||
#define PBC_INTR_SD3_EN 0x2000
|
||||
#define PBC_INTR_MS_EN 0x4000
|
||||
#define PBC_INTR_SD1_EN 0x8000
|
||||
|
||||
|
||||
|
||||
/* For interrupts like xuart, enet etc */
|
||||
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
|
||||
#define MXC_MAX_EXP_IO_LINES 16
|
||||
|
||||
/*
|
||||
* This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
|
||||
*
|
||||
*/
|
||||
#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
|
||||
#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
|
||||
#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
|
||||
#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
|
||||
#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
|
||||
#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
|
||||
#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
|
||||
#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
|
||||
#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
|
||||
#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
|
||||
#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
|
||||
#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
|
||||
#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
|
||||
#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
|
||||
#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
|
||||
|
||||
/*
|
||||
* This is System IRQ used by CS8900A for interrupt generation
|
||||
* taken from platform.h
|
||||
*/
|
||||
#define CS8900AIRQ EXPIO_INT_ENET_INT
|
||||
/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
|
||||
#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
|
||||
|
||||
#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
|
||||
|
||||
/*
|
||||
* This is used to detect if the CPLD version is for mx27 evb board rev-a
|
||||
*/
|
||||
#define PBC_CPLD_VERSION_IS_REVA() \
|
||||
((__raw_readw(PBC_VERSION_REG) & \
|
||||
(PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
|
||||
== 0)
|
||||
|
||||
/* This is used to active or inactive ata signal in CPLD .
|
||||
* It is dependent with hardware
|
||||
*/
|
||||
#define PBC_ATA_SIGNAL_ACTIVE() \
|
||||
__raw_writew( \
|
||||
PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
|
||||
PBC_BCTRL2_CLEAR_REG)
|
||||
|
||||
#define PBC_ATA_SIGNAL_INACTIVE() \
|
||||
__raw_writew( \
|
||||
PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
|
||||
PBC_BCTRL2_SET_REG)
|
||||
|
||||
#define MXC_BD_LED1 (1 << 5)
|
||||
#define MXC_BD_LED2 (1 << 6)
|
||||
#define MXC_BD_LED_ON(led) \
|
||||
__raw_writew(led, PBC_BCTRL1_SET_REG)
|
||||
#define MXC_BD_LED_OFF(led) \
|
||||
__raw_writew(led, PBC_BCTRL1_CLEAR_REG)
|
||||
|
||||
/* to determine the correct external crystal reference */
|
||||
#define CKIH_27MHZ_BIT_SET (1 << 3)
|
||||
|
||||
#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
|
||||
@ -22,7 +22,9 @@
|
||||
#ifdef CONFIG_MACH_MX31LITE
|
||||
#include <asm/arch/board-mx31lite.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MX27ADS
|
||||
#include <asm/arch/board-mx27ads.h>
|
||||
#endif
|
||||
.macro addruart,rx
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
|
||||
Loading…
Reference in New Issue
Block a user