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Fixed pin numbers for uart4 on rk3288, iommu clocks and small changes

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over multiple boards like default serial setting for rk3288-tinker,
 output selection for the dp83867 on the phycore-som and the newly
 added pwm-backlight delay properties for veyron boards.
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Merge tag 'v4.18-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Fixed pin numbers for uart4 on rk3288, iommu clocks and small changes
over multiple boards like default serial setting for rk3288-tinker,
output selection for the dp83867 on the phycore-som and the newly
added pwm-backlight delay properties for veyron boards.

* tag 'v4.18-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: default serial for rk3288 Tinker Board
  ARM: dts: rockchip: set PWM delay backlight settings for Minnie
  ARM: dts: rockchip: set PWM delay backlight settings for Veyron
  ARM: dts: rockchip: add clocks in iommu nodes
  ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som
  ARM: dts: rockchip: fix uart4 pin-numbers for rk3288

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-05-15 13:51:43 -07:00
commit 80dedbe0a8
7 changed files with 35 additions and 5 deletions
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2
arch/arm/boot/dts/rk3036.dtsi
View File

@ -197,6 +197,8 @@
reg = <0x10118300 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};

8
arch/arm/boot/dts/rk322x.dtsi
View File

@ -584,6 +584,8 @@
reg = <0x20020800 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
iommu-cells = <0>;
status = "disabled";
};
@ -593,6 +595,8 @@
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
iommu-cells = <0>;
status = "disabled";
};
@ -602,6 +606,8 @@
reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
iommu-cells = <0>;
status = "disabled";
};
@ -611,6 +617,8 @@
reg = <0x20070800 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
iommu-cells = <0>;
status = "disabled";
};

1
arch/arm/boot/dts/rk3288-phycore-som.dtsi
View File

@ -151,6 +151,7 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
};
};
};

4
arch/arm/boot/dts/rk3288-tinker.dts
View File

@ -49,6 +49,10 @@
model = "Rockchip RK3288 Tinker Board";
compatible = "asus,rk3288-tinker", "rockchip,rk3288";
chosen {
stdout-path = "serial2:115200n8";
};
memory {
reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";

3
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
View File

@ -95,7 +95,8 @@
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 0>;
pwm-delay-us = <10000>;
post-pwm-on-delay-ms = <10>;
pwm-off-delay-ms = <10>;
};
gpio-charger {

2
arch/arm/boot/dts/rk3288-veyron-minnie.dts
View File

@ -123,6 +123,8 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
power-supply = <&backlight_regulator>;
post-pwm-on-delay-ms = <200>;
pwm-off-delay-ms = <200>;
};
&emmc {

20
arch/arm/boot/dts/rk3288.dtsi
View File

@ -959,6 +959,8 @@
reg = <0x0 0xff900800 0x0 0x40>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -968,6 +970,8 @@
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_mmu";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
@ -1027,6 +1031,8 @@
reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk", "iface";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
@ -1075,6 +1081,8 @@
reg = <0x0 0xff940300 0x0 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "iface";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
@ -1206,6 +1214,8 @@
reg = <0x0 0xff9a0800 0x0 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -1215,6 +1225,8 @@
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -1848,16 +1860,16 @@
uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins = <5 12 3 &pcfg_pull_up>,
<5 13 3 &pcfg_pull_none>;
rockchip,pins = <5 15 3 &pcfg_pull_up>,
<5 14 3 &pcfg_pull_none>;
};
uart4_cts: uart4-cts {
rockchip,pins = <5 14 3 &pcfg_pull_up>;
rockchip,pins = <5 12 3 &pcfg_pull_up>;
};
uart4_rts: uart4-rts {
rockchip,pins = <5 15 3 &pcfg_pull_none>;
rockchip,pins = <5 13 3 &pcfg_pull_none>;
};
};