forked from Minki/linux
drm/amdgpu: refine uvd 5.0 clock gate feature.
1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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68260f340e
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809a6a62b6
@ -40,7 +40,10 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
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static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
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static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
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static int uvd_v5_0_start(struct amdgpu_device *adev);
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static int uvd_v5_0_start(struct amdgpu_device *adev);
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static void uvd_v5_0_stop(struct amdgpu_device *adev);
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static void uvd_v5_0_stop(struct amdgpu_device *adev);
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static int uvd_v5_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state);
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static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
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bool enable);
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/**
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/**
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* uvd_v5_0_ring_get_rptr - get read pointer
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* uvd_v5_0_ring_get_rptr - get read pointer
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*
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*
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@ -149,9 +152,6 @@ static int uvd_v5_0_hw_init(void *handle)
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uint32_t tmp;
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uint32_t tmp;
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int r;
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int r;
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/* raise clocks while booting up the VCPU */
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amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
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r = uvd_v5_0_start(adev);
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r = uvd_v5_0_start(adev);
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if (r)
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if (r)
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goto done;
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goto done;
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@ -189,11 +189,7 @@ static int uvd_v5_0_hw_init(void *handle)
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amdgpu_ring_write(ring, 3);
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amdgpu_ring_write(ring, 3);
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amdgpu_ring_commit(ring);
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amdgpu_ring_commit(ring);
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done:
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done:
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/* lower clocks again */
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amdgpu_asic_set_uvd_clocks(adev, 0, 0);
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if (!r)
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if (!r)
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DRM_INFO("UVD initialized successfully.\n");
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DRM_INFO("UVD initialized successfully.\n");
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@ -226,6 +222,7 @@ static int uvd_v5_0_suspend(void *handle)
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r = uvd_v5_0_hw_fini(adev);
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r = uvd_v5_0_hw_fini(adev);
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if (r)
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if (r)
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return r;
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return r;
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uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
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r = amdgpu_uvd_suspend(adev);
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r = amdgpu_uvd_suspend(adev);
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if (r)
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if (r)
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@ -313,8 +310,9 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
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uvd_v5_0_mc_resume(adev);
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uvd_v5_0_mc_resume(adev);
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/* disable clock gating */
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amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
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WREG32(mmUVD_CGC_GATE, 0);
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uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
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uvd_v5_0_enable_mgcg(adev, true);
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/* disable interupt */
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/* disable interupt */
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WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
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WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
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@ -628,16 +626,12 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
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return 0;
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return 0;
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}
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}
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static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
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static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
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{
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{
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uint32_t data, data1, data2, suvd_flags;
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uint32_t data1, data3, suvd_flags;
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data = RREG32(mmUVD_CGC_CTRL);
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data1 = RREG32(mmUVD_SUVD_CGC_GATE);
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data1 = RREG32(mmUVD_SUVD_CGC_GATE);
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data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
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data3 = RREG32(mmUVD_CGC_GATE);
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data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
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UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
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suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
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suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
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UVD_SUVD_CGC_GATE__SIT_MASK |
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UVD_SUVD_CGC_GATE__SIT_MASK |
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@ -645,6 +639,49 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
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UVD_SUVD_CGC_GATE__SCM_MASK |
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UVD_SUVD_CGC_GATE__SCM_MASK |
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UVD_SUVD_CGC_GATE__SDB_MASK;
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UVD_SUVD_CGC_GATE__SDB_MASK;
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if (enable) {
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data3 |= (UVD_CGC_GATE__SYS_MASK |
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UVD_CGC_GATE__UDEC_MASK |
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UVD_CGC_GATE__MPEG2_MASK |
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UVD_CGC_GATE__RBC_MASK |
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UVD_CGC_GATE__LMI_MC_MASK |
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UVD_CGC_GATE__IDCT_MASK |
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UVD_CGC_GATE__MPRD_MASK |
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UVD_CGC_GATE__MPC_MASK |
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UVD_CGC_GATE__LBSI_MASK |
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UVD_CGC_GATE__LRBBM_MASK |
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UVD_CGC_GATE__UDEC_RE_MASK |
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UVD_CGC_GATE__UDEC_CM_MASK |
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UVD_CGC_GATE__UDEC_IT_MASK |
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UVD_CGC_GATE__UDEC_DB_MASK |
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UVD_CGC_GATE__UDEC_MP_MASK |
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UVD_CGC_GATE__WCB_MASK |
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UVD_CGC_GATE__VCPU_MASK |
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UVD_CGC_GATE__JPEG_MASK |
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UVD_CGC_GATE__SCPU_MASK);
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data3 &= ~UVD_CGC_GATE__REGS_MASK;
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data1 |= suvd_flags;
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} else {
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data3 = 0;
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data1 = 0;
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}
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WREG32(mmUVD_SUVD_CGC_GATE, data1);
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WREG32(mmUVD_CGC_GATE, data3);
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}
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static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
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{
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uint32_t data, data2;
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data = RREG32(mmUVD_CGC_CTRL);
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data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
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data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
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UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
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data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
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data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
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(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
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(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
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(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
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(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
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@ -675,11 +712,8 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
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UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
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UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
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UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
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UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
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UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
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UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
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data1 |= suvd_flags;
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WREG32(mmUVD_CGC_CTRL, data);
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WREG32(mmUVD_CGC_CTRL, data);
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WREG32(mmUVD_CGC_GATE, 0);
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WREG32(mmUVD_SUVD_CGC_GATE, data1);
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WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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}
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}
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@ -724,6 +758,31 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
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}
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}
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#endif
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#endif
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static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
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bool enable)
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{
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u32 orig, data;
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
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data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
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data |= 0xfff;
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WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
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orig = data = RREG32(mmUVD_CGC_CTRL);
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data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
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if (orig != data)
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WREG32(mmUVD_CGC_CTRL, data);
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} else {
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data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
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data &= ~0xfff;
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WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
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orig = data = RREG32(mmUVD_CGC_CTRL);
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data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
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if (orig != data)
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WREG32(mmUVD_CGC_CTRL, data);
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}
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}
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static int uvd_v5_0_set_clockgating_state(void *handle,
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static int uvd_v5_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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enum amd_clockgating_state state)
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@ -740,17 +799,18 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
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curstate = state;
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curstate = state;
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if (enable) {
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if (enable) {
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/* disable HW gating and enable Sw gating */
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uvd_v5_0_set_sw_clock_gating(adev);
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} else {
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/* wait for STATUS to clear */
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/* wait for STATUS to clear */
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if (uvd_v5_0_wait_for_idle(handle))
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if (uvd_v5_0_wait_for_idle(handle))
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return -EBUSY;
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return -EBUSY;
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uvd_v5_0_enable_clock_gating(adev, true);
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/* enable HW gates because UVD is idle */
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/* enable HW gates because UVD is idle */
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/* uvd_v5_0_set_hw_clock_gating(adev); */
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/* uvd_v5_0_set_hw_clock_gating(adev); */
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} else {
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uvd_v5_0_enable_clock_gating(adev, false);
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}
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}
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uvd_v5_0_set_sw_clock_gating(adev);
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return 0;
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return 0;
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}
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}
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