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drm/amd/display: fix DP 422 VID_M half the rate issue.

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[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as  YCbCr444.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2019-03-01 11:12:50 -05:00 committed by Alex Deucher
parent ae5041f3a0
commit 7fe538a4d6
5 changed files with 31 additions and 9 deletions
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2
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View File

@ -977,7 +977,7 @@ static void dce110_stream_encoder_dp_unblank(
uint64_t m_vid_l = n_vid;
m_vid_l *= param->pixel_clk_khz;
m_vid_l *= param->timing.pix_clk_100hz / 10;
m_vid_l = div_u64(m_vid_l,
param->link_settings.link_rate
* LINK_RATE_REF_FREQ_IN_KHZ);

3
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1052,9 +1052,8 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
struct dc_link *link = stream->link;
/* only 3 items below are used by unblank */
params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
params.timing = pipe_ctx->stream->timing;
params.link_settings.link_rate = link_settings->link_rate;
params.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);

25
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2900,6 +2900,29 @@ static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
tg->funcs->setup_vertical_interrupt2(tg, start_line);
}
static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings)
{
struct encoder_unblank_param params = { { 0 } };
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
/* only 3 items below are used by unblank */
params.timing = pipe_ctx->stream->timing;
params.link_settings.link_rate = link_settings->link_rate;
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
params.timing.pix_clk_100hz /= 2;
pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
}
if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
link->dc->hwss.edp_backlight_control(link, true);
}
}
static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
.init_hw = dcn10_init_hw,
@ -2921,7 +2944,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.update_info_frame = dce110_update_info_frame,
.enable_stream = dce110_enable_stream,
.disable_stream = dce110_disable_stream,
.unblank_stream = dce110_unblank_stream,
.unblank_stream = dcn10_unblank_stream,
.blank_stream = dce110_blank_stream,
.enable_audio_stream = dce110_enable_audio_stream,
.disable_audio_stream = dce110_disable_audio_stream,

7
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
View File

@ -836,14 +836,15 @@ void enc1_stream_encoder_dp_unblank(
uint64_t m_vid_l = n_vid;
/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
if (param->pixel_encoding == PIXEL_ENCODING_YCBCR420)
if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
/*this param->pixel_clk_khz is half of 444 rate for 420 already*/
n_multiply = 1;
}
/* M / N = Fstream / Flink
* m_vid / n_vid = pixel rate / link rate
*/
m_vid_l *= param->pixel_clk_khz;
m_vid_l *= param->timing.pix_clk_100hz / 10;
m_vid_l = div_u64(m_vid_l,
param->link_settings.link_rate
* LINK_RATE_REF_FREQ_IN_KHZ);

3
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View File

@ -67,8 +67,7 @@ struct encoder_info_frame {
struct encoder_unblank_param {
struct dc_link_settings link_settings;
unsigned int pixel_clk_khz;
enum dc_pixel_encoding pixel_encoding;
struct dc_crtc_timing timing;
};
struct encoder_set_dp_phy_pattern_param {