forked from Minki/linux
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next
This commit is contained in:
commit
7f83560df2
@ -1759,6 +1759,7 @@ static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
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skb->data, skb->len, PCI_DMA_TODEVICE));
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/* check for mapping failure? */
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cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
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skb_tx_timestamp(skb);
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}
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static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
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@ -2733,6 +2734,7 @@ static const struct ethtool_ops e100_ethtool_ops = {
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.set_phys_id = e100_set_phys_id,
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.get_ethtool_stats = e100_get_ethtool_stats,
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.get_sset_count = e100_get_sset_count,
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.get_ts_info = ethtool_op_get_ts_info,
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};
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static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
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|
@ -228,9 +228,7 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
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/* FWSM register */
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mac->has_fwsm = true;
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/* ARC supported; valid only if manageability features are enabled. */
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mac->arc_subsystem_valid =
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(er32(FWSM) & E1000_FWSM_MODE_MASK)
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? true : false;
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mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
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/* Adaptive IFS not supported */
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mac->adaptive_ifs = false;
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@ -295,9 +295,8 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
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* ARC supported; valid only if manageability features are
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* enabled.
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*/
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mac->arc_subsystem_valid =
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(er32(FWSM) & E1000_FWSM_MODE_MASK)
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? true : false;
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mac->arc_subsystem_valid = !!(er32(FWSM) &
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E1000_FWSM_MODE_MASK);
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break;
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case e1000_82574:
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case e1000_82583:
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@ -798,7 +797,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
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/* Check for pending operations. */
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for (i = 0; i < E1000_FLASH_UPDATES; i++) {
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usleep_range(1000, 2000);
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if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
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if (!(er32(EECD) & E1000_EECD_FLUPD))
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break;
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}
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@ -822,7 +821,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
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for (i = 0; i < E1000_FLASH_UPDATES; i++) {
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usleep_range(1000, 2000);
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if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
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if (!(er32(EECD) & E1000_EECD_FLUPD))
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break;
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}
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@ -259,8 +259,7 @@ static int e1000_set_settings(struct net_device *netdev,
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* cannot be changed
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*/
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if (hw->phy.ops.check_reset_block(hw)) {
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e_err("Cannot change link characteristics when SoL/IDER is "
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"active.\n");
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e_err("Cannot change link characteristics when SoL/IDER is active.\n");
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return -EINVAL;
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}
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@ -727,9 +726,8 @@ static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
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(test[pat] & write));
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val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset);
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if (val != (test[pat] & write & mask)) {
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e_err("pattern test reg %04X failed: got 0x%08X "
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"expected 0x%08X\n", reg + offset, val,
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(test[pat] & write & mask));
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e_err("pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
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reg + offset, val, (test[pat] & write & mask));
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*data = reg;
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return 1;
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}
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@ -744,8 +742,8 @@ static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data,
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__ew32(&adapter->hw, reg, write & mask);
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val = __er32(&adapter->hw, reg);
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if ((write & mask) != (val & mask)) {
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e_err("set/check reg %04X test failed: got 0x%08X "
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"expected 0x%08X\n", reg, (val & mask), (write & mask));
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e_err("set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
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reg, (val & mask), (write & mask));
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*data = reg;
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return 1;
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}
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@ -797,8 +795,8 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
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ew32(STATUS, toggle);
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after = er32(STATUS) & toggle;
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if (value != after) {
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e_err("failed STATUS register test got: 0x%08X expected: "
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"0x%08X\n", after, value);
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e_err("failed STATUS register test got: 0x%08X expected: 0x%08X\n",
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after, value);
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*data = 1;
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return 1;
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}
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@ -1791,8 +1789,7 @@ static void e1000_get_wol(struct net_device *netdev,
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wol->supported &= ~WAKE_UCAST;
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if (adapter->wol & E1000_WUFC_EX)
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e_err("Interface does not support directed (unicast) "
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"frame wake-up packets\n");
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e_err("Interface does not support directed (unicast) frame wake-up packets\n");
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}
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if (adapter->wol & E1000_WUFC_EX)
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@ -2212,7 +2212,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
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hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
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/* Check if the flash descriptor is valid */
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if (hsfsts.hsf_status.fldesvalid == 0) {
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if (!hsfsts.hsf_status.fldesvalid) {
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e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
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return -E1000_ERR_NVM;
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}
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@ -2232,7 +2232,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
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* completed.
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*/
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if (hsfsts.hsf_status.flcinprog == 0) {
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if (!hsfsts.hsf_status.flcinprog) {
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/*
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* There is no cycle running at present,
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* so we can start a cycle.
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@ -2250,7 +2250,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
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*/
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for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
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hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
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if (hsfsts.hsf_status.flcinprog == 0) {
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if (!hsfsts.hsf_status.flcinprog) {
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ret_val = 0;
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break;
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}
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@ -2292,12 +2292,12 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
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/* wait till FDONE bit is set to 1 */
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do {
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hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
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if (hsfsts.hsf_status.flcdone == 1)
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if (hsfsts.hsf_status.flcdone)
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break;
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udelay(1);
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} while (i++ < timeout);
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if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
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if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
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return 0;
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return -E1000_ERR_NVM;
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@ -2408,10 +2408,10 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
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* ICH_FLASH_CYCLE_REPEAT_COUNT times.
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*/
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hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
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if (hsfsts.hsf_status.flcerr == 1) {
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if (hsfsts.hsf_status.flcerr) {
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/* Repeat for some time before giving up. */
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continue;
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} else if (hsfsts.hsf_status.flcdone == 0) {
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} else if (!hsfsts.hsf_status.flcdone) {
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e_dbg("Timeout error - flash cycle did not complete.\n");
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break;
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}
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@ -2641,7 +2641,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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if ((data & 0x40) == 0) {
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if (!(data & 0x40)) {
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data |= 0x40;
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ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
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if (ret_val)
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@ -2759,10 +2759,10 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
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* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
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*/
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hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
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if (hsfsts.hsf_status.flcerr == 1)
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if (hsfsts.hsf_status.flcerr)
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/* Repeat for some time before giving up. */
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continue;
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if (hsfsts.hsf_status.flcdone == 0) {
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if (!hsfsts.hsf_status.flcdone) {
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e_dbg("Timeout error - flash cycle did not complete.\n");
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break;
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}
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@ -2914,10 +2914,10 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
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* a few more times else Done
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*/
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hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
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if (hsfsts.hsf_status.flcerr == 1)
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if (hsfsts.hsf_status.flcerr)
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/* repeat for some time before giving up */
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continue;
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else if (hsfsts.hsf_status.flcdone == 0)
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else if (!hsfsts.hsf_status.flcdone)
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return ret_val;
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} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
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}
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@ -3916,7 +3916,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
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/* If EEPROM is not marked present, init the IGP 3 PHY manually */
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if (hw->mac.type <= e1000_ich9lan) {
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if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
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if (!(er32(EECD) & E1000_EECD_PRES) &&
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(hw->phy.type == e1000_phy_igp_3)) {
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e1000e_phy_init_script_igp3(hw);
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}
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@ -681,7 +681,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
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return ret_val;
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}
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if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
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if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
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hw->fc.requested_mode = e1000_fc_none;
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else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
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hw->fc.requested_mode = e1000_fc_tx_pause;
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@ -85,7 +85,7 @@ static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
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/* Check that the host interface is enabled. */
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hicr = er32(HICR);
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if ((hicr & E1000_HICR_EN) == 0) {
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if (!(hicr & E1000_HICR_EN)) {
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e_dbg("E1000_HOST_EN bit disabled.\n");
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return -E1000_ERR_HOST_INTERFACE_COMMAND;
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}
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|
@ -166,8 +166,8 @@ E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lea
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*
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* Default Value: 1 (enabled)
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*/
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E1000_PARAM(CrcStripping, "Enable CRC Stripping, disable if your BMC needs " \
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"the CRC");
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E1000_PARAM(CrcStripping,
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"Enable CRC Stripping, disable if your BMC needs the CRC");
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struct e1000_option {
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enum { enable_option, range_option, list_option } type;
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@ -360,8 +360,8 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
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adapter->itr = 20000;
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break;
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case 4:
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e_info("%s set to simplified (2000-8000 ints) "
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"mode\n", opt.name);
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e_info("%s set to simplified (2000-8000 ints) mode\n",
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opt.name);
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adapter->itr_setting = 4;
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break;
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default:
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|
@ -718,7 +718,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
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* 1 - Enabled
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*/
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phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
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if (phy->disable_polarity_correction == 1)
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if (phy->disable_polarity_correction)
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phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
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/* Enable downshift on BM (disabled by default) */
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@ -1090,7 +1090,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
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* If autoneg_advertised is zero, we assume it was not defaulted
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* by the calling code so we set to advertise full capability.
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*/
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if (phy->autoneg_advertised == 0)
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if (!phy->autoneg_advertised)
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phy->autoneg_advertised = phy->autoneg_mask;
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e_dbg("Reconfiguring auto-neg advertisement params\n");
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@ -1596,7 +1596,7 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
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ret_val = e1e_rphy(hw, offset, &phy_data);
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if (!ret_val)
|
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phy->speed_downgraded = (phy_data & mask);
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phy->speed_downgraded = !!(phy_data & mask);
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return ret_val;
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}
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@ -1925,8 +1925,8 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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|
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phy->polarity_correction = (phy_data &
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M88E1000_PSCR_POLARITY_REVERSAL);
|
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phy->polarity_correction = !!(phy_data &
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||||
M88E1000_PSCR_POLARITY_REVERSAL);
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ret_val = e1000_check_polarity_m88(hw);
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if (ret_val)
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@ -1936,7 +1936,7 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
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if (ret_val)
|
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return ret_val;
|
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phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
|
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phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
|
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|
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if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
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ret_val = e1000_get_cable_length(hw);
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@ -1999,7 +1999,7 @@ s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
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if (ret_val)
|
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return ret_val;
|
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phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
|
||||
phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
|
||||
|
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if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
|
||||
IGP01E1000_PSSR_SPEED_1000MBPS) {
|
||||
@ -2052,8 +2052,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
|
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ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
|
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if (ret_val)
|
||||
return ret_val;
|
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phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
|
||||
? false : true;
|
||||
phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
|
||||
|
||||
if (phy->polarity_correction) {
|
||||
ret_val = e1000_check_polarity_ife(hw);
|
||||
@ -2070,7 +2069,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
|
||||
phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
|
||||
|
||||
/* The following parameters are undefined for 10/100 operation. */
|
||||
phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
|
||||
@ -2979,7 +2978,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
|
||||
if ((hw->phy.type == e1000_phy_82578) &&
|
||||
(hw->phy.revision >= 1) &&
|
||||
(hw->phy.addr == 2) &&
|
||||
((MAX_PHY_REG_ADDRESS & reg) == 0) && (data & (1 << 11))) {
|
||||
!(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
|
||||
u16 data2 = 0x7EFF;
|
||||
ret_val = e1000_access_phy_debug_regs_hv(hw,
|
||||
(1 << 6) | 0x3,
|
||||
@ -3265,7 +3264,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
|
||||
phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
|
||||
|
||||
if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
|
||||
I82577_PHY_STATUS2_SPEED_1000MBPS) {
|
||||
|
@ -60,8 +60,8 @@
|
||||
#include "igb.h"
|
||||
|
||||
#define MAJ 3
|
||||
#define MIN 2
|
||||
#define BUILD 10
|
||||
#define MIN 4
|
||||
#define BUILD 7
|
||||
#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
|
||||
__stringify(BUILD) "-k"
|
||||
char igb_driver_name[] = "igb";
|
||||
|
@ -1582,13 +1582,21 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
|
||||
**/
|
||||
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
||||
{
|
||||
*i2cctl |= IXGBE_I2C_CLK_OUT;
|
||||
u32 i = 0;
|
||||
u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
|
||||
u32 i2cctl_r = 0;
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
for (i = 0; i < timeout; i++) {
|
||||
*i2cctl |= IXGBE_I2C_CLK_OUT;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
/* SCL rise time (1000ns) */
|
||||
udelay(IXGBE_I2C_T_RISE);
|
||||
|
||||
/* SCL rise time (1000ns) */
|
||||
udelay(IXGBE_I2C_T_RISE);
|
||||
i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
if (i2cctl_r & IXGBE_I2C_CLK_IN)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -110,6 +110,7 @@
|
||||
#define IXGBE_I2C_CLK_OUT 0x00000002
|
||||
#define IXGBE_I2C_DATA_IN 0x00000004
|
||||
#define IXGBE_I2C_DATA_OUT 0x00000008
|
||||
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
|
||||
|
||||
/* Interrupt Registers */
|
||||
#define IXGBE_EICR 0x00800
|
||||
|
Loading…
Reference in New Issue
Block a user