dt-bindings: bus: Convert UniPhier System Bus to json-schema
Convert the UniPhier System Bus controller binding to DT schema format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Rob Herring <robh@kernel.org>
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Masahiro Yamada
Rob Herring
parent
849b10446b
commit
7f44205eb2
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: UniPhier System Bus
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description: |
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The UniPhier System Bus is an external bus that connects on-board devices to
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the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
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some control signals. It supports up to 8 banks (chip selects).
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Before any access to the bus, the bus controller must be configured; the bus
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controller registers provide the control for the translation from the offset
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within each bank to the CPU-viewed address. The needed setup includes the
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base address, the size of each bank. Optionally, some timing parameters can
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be optimized for faster bus access.
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maintainers:
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- Masahiro Yamada <yamada.masahiro@socionext.com>
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properties:
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compatible:
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const: socionext,uniphier-system-bus
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reg:
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maxItems: 1
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"#address-cells":
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description: |
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The first cell is the bank number (chip select).
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The second cell is the address offset within the bank.
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const: 2
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"#size-cells":
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const: 1
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ranges:
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description: |
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Provide address translation from the System Bus to the parent bus.
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Note:
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The address region(s) that can be assigned for the System Bus is
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implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
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0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
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There might be additional limitations depending on SoCs and the boot mode.
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The address translation is arbitrary as long as the banks are assigned in
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the supported address space with the required alignment and they do not
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overlap one another.
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For example, it is possible to map:
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bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
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It is also possible to map:
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bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
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There is no reason to stick to a particular translation mapping, but the
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"ranges" property should provide a "reasonable" default that is known to
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work. The software should initialize the bus controller according to it.
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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examples:
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- |
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// In this example,
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// - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
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// mapped to 0x43f00000 of the parent bus.
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// - the UART device is connected at the offset 0x00200000 of CS5 and
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// mapped to 0x46200000 of the parent bus.
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system-bus {
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compatible = "socionext,uniphier-system-bus";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <1 0x00000000 0x42000000 0x02000000>,
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<5 0x00000000 0x46000000 0x01000000>;
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ethernet@1,01f00000 {
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compatible = "smsc,lan9115";
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reg = <1 0x01f00000 0x1000>;
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interrupts = <0 48 4>;
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phy-mode = "mii";
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};
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uart@5,00200000 {
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compatible = "ns16550a";
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reg = <5 0x00200000 0x20>;
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interrupts = <0 49 4>;
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clock-frequency = <12288000>;
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};
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};
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@ -1,66 +0,0 @@
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UniPhier System Bus
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The UniPhier System Bus is an external bus that connects on-board devices to
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the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
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some control signals. It supports up to 8 banks (chip selects).
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Before any access to the bus, the bus controller must be configured; the bus
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controller registers provide the control for the translation from the offset
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within each bank to the CPU-viewed address. The needed setup includes the base
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address, the size of each bank. Optionally, some timing parameters can be
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optimized for faster bus access.
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Required properties:
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- compatible: should be "socionext,uniphier-system-bus".
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- reg: offset and length of the register set for the bus controller device.
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- #address-cells: should be 2. The first cell is the bank number (chip select).
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The second cell is the address offset within the bank.
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- #size-cells: should be 1.
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- ranges: should provide a proper address translation from the System Bus to
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the parent bus.
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Note:
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The address region(s) that can be assigned for the System Bus is implementation
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defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
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while other SoCs can only use 0x40000000-0x4fffffff. There might be additional
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limitations depending on SoCs and the boot mode. The address translation is
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arbitrary as long as the banks are assigned in the supported address space with
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the required alignment and they do not overlap one another.
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For example, it is possible to map:
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bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
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It is also possible to map:
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bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
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There is no reason to stick to a particular translation mapping, but the
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"ranges" property should provide a "reasonable" default that is known to work.
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The software should initialize the bus controller according to it.
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Example:
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system-bus {
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compatible = "socionext,uniphier-system-bus";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <1 0x00000000 0x42000000 0x02000000
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5 0x00000000 0x46000000 0x01000000>;
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ethernet@1,01f00000 {
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compatible = "smsc,lan9115";
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reg = <1 0x01f00000 0x1000>;
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interrupts = <0 48 4>
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phy-mode = "mii";
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};
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uart@5,00200000 {
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compatible = "ns16550a";
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reg = <5 0x00200000 0x20>;
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interrupts = <0 49 4>
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clock-frequency = <12288000>;
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};
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};
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In this example,
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- the Ethernet device is connected at the offset 0x01f00000 of CS1 and
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mapped to 0x43f00000 of the parent bus.
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- the UART device is connected at the offset 0x00200000 of CS5 and
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mapped to 0x46200000 of the parent bus.
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