nfp: take chip version into account for ring sizes

NFP3800 has slightly different queue controller range bounds.
Use the static chip data instead of defines.  This commit
still assumes unchanged descriptor format.  Later datapath
changes will allow adjusting for descriptor accounting.

Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Fei Qin <fei.qin@corigine.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2022-03-11 11:43:05 +01:00
committed by Jakub Kicinski
parent e900db704c
commit 7f3aa620f8
4 changed files with 16 additions and 10 deletions

View File

@@ -82,11 +82,6 @@
NFP_NET_MAX_TX_RINGS : NFP_NET_MAX_RX_RINGS) NFP_NET_MAX_TX_RINGS : NFP_NET_MAX_RX_RINGS)
#define NFP_NET_MAX_IRQS (NFP_NET_NON_Q_VECTORS + NFP_NET_MAX_R_VECS) #define NFP_NET_MAX_IRQS (NFP_NET_NON_Q_VECTORS + NFP_NET_MAX_R_VECS)
#define NFP_NET_MIN_TX_DESCS 256 /* Min. # of Tx descs per ring */
#define NFP_NET_MIN_RX_DESCS 256 /* Min. # of Rx descs per ring */
#define NFP_NET_MAX_TX_DESCS (256 * 1024) /* Max. # of Tx descs per ring */
#define NFP_NET_MAX_RX_DESCS (256 * 1024) /* Max. # of Rx descs per ring */
#define NFP_NET_TX_DESCS_DEFAULT 4096 /* Default # of Tx descs per ring */ #define NFP_NET_TX_DESCS_DEFAULT 4096 /* Default # of Tx descs per ring */
#define NFP_NET_RX_DESCS_DEFAULT 4096 /* Default # of Rx descs per ring */ #define NFP_NET_RX_DESCS_DEFAULT 4096 /* Default # of Rx descs per ring */

View File

@@ -21,6 +21,7 @@
#include <linux/sfp.h> #include <linux/sfp.h>
#include "nfpcore/nfp.h" #include "nfpcore/nfp.h"
#include "nfpcore/nfp_dev.h"
#include "nfpcore/nfp_nsp.h" #include "nfpcore/nfp_nsp.h"
#include "nfp_app.h" #include "nfp_app.h"
#include "nfp_main.h" #include "nfp_main.h"
@@ -386,9 +387,10 @@ static void nfp_net_get_ringparam(struct net_device *netdev,
struct netlink_ext_ack *extack) struct netlink_ext_ack *extack)
{ {
struct nfp_net *nn = netdev_priv(netdev); struct nfp_net *nn = netdev_priv(netdev);
u32 qc_max = nn->dev_info->max_qc_size;
ring->rx_max_pending = NFP_NET_MAX_RX_DESCS; ring->rx_max_pending = qc_max;
ring->tx_max_pending = NFP_NET_MAX_TX_DESCS; ring->tx_max_pending = qc_max;
ring->rx_pending = nn->dp.rxd_cnt; ring->rx_pending = nn->dp.rxd_cnt;
ring->tx_pending = nn->dp.txd_cnt; ring->tx_pending = nn->dp.txd_cnt;
} }
@@ -413,18 +415,20 @@ static int nfp_net_set_ringparam(struct net_device *netdev,
struct netlink_ext_ack *extack) struct netlink_ext_ack *extack)
{ {
struct nfp_net *nn = netdev_priv(netdev); struct nfp_net *nn = netdev_priv(netdev);
u32 rxd_cnt, txd_cnt; u32 qc_min, qc_max, rxd_cnt, txd_cnt;
/* We don't have separate queues/rings for small/large frames. */ /* We don't have separate queues/rings for small/large frames. */
if (ring->rx_mini_pending || ring->rx_jumbo_pending) if (ring->rx_mini_pending || ring->rx_jumbo_pending)
return -EINVAL; return -EINVAL;
qc_min = nn->dev_info->min_qc_size;
qc_max = nn->dev_info->max_qc_size;
/* Round up to supported values */ /* Round up to supported values */
rxd_cnt = roundup_pow_of_two(ring->rx_pending); rxd_cnt = roundup_pow_of_two(ring->rx_pending);
txd_cnt = roundup_pow_of_two(ring->tx_pending); txd_cnt = roundup_pow_of_two(ring->tx_pending);
if (rxd_cnt < NFP_NET_MIN_RX_DESCS || rxd_cnt > NFP_NET_MAX_RX_DESCS || if (rxd_cnt < qc_min || rxd_cnt > qc_max ||
txd_cnt < NFP_NET_MIN_TX_DESCS || txd_cnt > NFP_NET_MAX_TX_DESCS) txd_cnt < qc_min || txd_cnt > qc_max)
return -EINVAL; return -EINVAL;
if (nn->dp.rxd_cnt == rxd_cnt && nn->dp.txd_cnt == txd_cnt) if (nn->dp.rxd_cnt == rxd_cnt && nn->dp.txd_cnt == txd_cnt)

View File

@@ -3,6 +3,7 @@
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/sizes.h>
#include "nfp_dev.h" #include "nfp_dev.h"
@@ -11,6 +12,8 @@ const struct nfp_dev_info nfp_dev_info[NFP_DEV_CNT] = {
.dma_mask = DMA_BIT_MASK(40), .dma_mask = DMA_BIT_MASK(40),
.qc_idx_mask = GENMASK(7, 0), .qc_idx_mask = GENMASK(7, 0),
.qc_addr_offset = 0x80000, .qc_addr_offset = 0x80000,
.min_qc_size = 256,
.max_qc_size = SZ_256K,
.chip_names = "NFP4000/NFP5000/NFP6000", .chip_names = "NFP4000/NFP5000/NFP6000",
.pcie_cfg_expbar_offset = 0x0400, .pcie_cfg_expbar_offset = 0x0400,
@@ -21,5 +24,7 @@ const struct nfp_dev_info nfp_dev_info[NFP_DEV_CNT] = {
.dma_mask = DMA_BIT_MASK(40), .dma_mask = DMA_BIT_MASK(40),
.qc_idx_mask = GENMASK(7, 0), .qc_idx_mask = GENMASK(7, 0),
.qc_addr_offset = 0, .qc_addr_offset = 0,
.min_qc_size = 256,
.max_qc_size = SZ_256K,
}, },
}; };

View File

@@ -17,6 +17,8 @@ struct nfp_dev_info {
u64 dma_mask; u64 dma_mask;
u32 qc_idx_mask; u32 qc_idx_mask;
u32 qc_addr_offset; u32 qc_addr_offset;
u32 min_qc_size;
u32 max_qc_size;
/* PF-only fields */ /* PF-only fields */
const char *chip_names; const char *chip_names;