forked from Minki/linux
dt-bindings: net: dsa: convert ocelot.txt to dt-schema
Replace the free-form description of device tree bindings for VSC9959 and VSC9953 with a YAML formatted dt-schema description. This contains more or less the same information, but reworded to be a bit more succint. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Maxim Kochetkov <fido_max@inbox.ru> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220913125806.524314-1-vladimir.oltean@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Vladimir Oltean
Jakub Kicinski
parent
93ece9a6de
commit
7f32974bdc
260
Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml
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260
Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR MIT)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Ocelot Switch Family Device Tree Bindings
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maintainers:
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- Vladimir Oltean <vladimir.oltean@nxp.com>
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- Claudiu Manoil <claudiu.manoil@nxp.com>
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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- UNGLinuxDriver@microchip.com
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description: |
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There are multiple switches which are either part of the Ocelot-1 family, or
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derivatives of this architecture. These switches can be found embedded in
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various SoCs and accessed using MMIO, or as discrete chips and accessed over
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SPI or PCIe. The present DSA binding shall be used when the host controlling
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them performs packet I/O primarily through an Ethernet port of the switch
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(which is attached to an Ethernet port of the host), rather than through
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Frame DMA or register-based I/O.
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VSC9953 (Seville):
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This is found in the NXP T1040, where it is a memory-mapped platform
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device.
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The following PHY interface types are supported:
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- phy-mode = "internal": on ports 8 and 9
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- phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
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- phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
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- phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7
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VSC9959 (Felix):
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This is found in the NXP LS1028A. It is a PCI device, part of the larger
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enetc root complex. As a result, the ethernet-switch node is a sub-node of
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the PCIe root complex node and its "reg" property conforms to the parent
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node bindings, describing it as PF 5 of device 0, bus 0.
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If any external switch port is enabled, the enetc PF2 (enetc_port2) should
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be enabled as well. This is because the internal MDIO bus (exposed through
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EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
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port 2 and not to Felix.
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The following PHY interface types are supported:
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- phy-mode = "internal": on ports 4 and 5
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- phy-mode = "sgmii": on ports 0, 1, 2, 3
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- phy-mode = "qsgmii": on ports 0, 1, 2, 3
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- phy-mode = "usxgmii": on ports 0, 1, 2, 3
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- phy-mode = "1000base-x": on ports 0, 1, 2, 3
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- phy-mode = "2500base-x": on ports 0, 1, 2, 3
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properties:
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compatible:
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enum:
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- mscc,vsc9953-switch
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- pci1957,eef0
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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description:
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Used to signal availability of PTP TX timestamps, and state changes of
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the MAC merge layer of ports that support Frame Preemption.
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little-endian: true
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big-endian: true
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required:
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- compatible
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- reg
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allOf:
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- $ref: dsa.yaml#
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- if:
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properties:
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compatible:
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const: pci1957,eef0
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then:
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required:
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- interrupts
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unevaluatedProperties: false
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examples:
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# Felix VSC9959 (NXP LS1028A)
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie { /* Integrated Endpoint Root Complex */
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#address-cells = <3>;
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#size-cells = <2>;
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ethernet-switch@0,5 {
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compatible = "pci1957,eef0";
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reg = <0x000500 0 0 0 0>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phy-mode = "qsgmii";
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phy-handle = <&phy0>;
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managed = "in-band-status";
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};
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port@1 {
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reg = <1>;
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phy-mode = "qsgmii";
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phy-handle = <&phy1>;
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managed = "in-band-status";
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};
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port@2 {
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reg = <2>;
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phy-mode = "qsgmii";
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phy-handle = <&phy2>;
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managed = "in-band-status";
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};
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port@3 {
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reg = <3>;
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phy-mode = "qsgmii";
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phy-handle = <&phy3>;
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managed = "in-band-status";
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};
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port@4 {
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reg = <4>;
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ethernet = <&enetc_port2>;
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phy-mode = "internal";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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port@5 {
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reg = <5>;
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ethernet = <&enetc_port3>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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# Seville VSC9953 (NXP T1040)
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- |
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ethernet-switch@800000 {
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compatible = "mscc,vsc9953-switch";
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reg = <0x800000 0x290000>;
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little-endian;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phy-mode = "qsgmii";
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phy-handle = <&phy0>;
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managed = "in-band-status";
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};
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port@1 {
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reg = <1>;
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phy-mode = "qsgmii";
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phy-handle = <&phy1>;
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managed = "in-band-status";
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};
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port@2 {
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reg = <2>;
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phy-mode = "qsgmii";
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phy-handle = <&phy2>;
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managed = "in-band-status";
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};
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port@3 {
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reg = <3>;
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phy-mode = "qsgmii";
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phy-handle = <&phy3>;
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managed = "in-band-status";
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};
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port@4 {
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reg = <4>;
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phy-mode = "qsgmii";
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phy-handle = <&phy4>;
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managed = "in-band-status";
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};
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port@5 {
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reg = <5>;
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phy-mode = "qsgmii";
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phy-handle = <&phy5>;
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managed = "in-band-status";
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};
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port@6 {
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reg = <6>;
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phy-mode = "qsgmii";
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phy-handle = <&phy6>;
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managed = "in-band-status";
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};
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port@7 {
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reg = <7>;
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phy-mode = "qsgmii";
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phy-handle = <&phy7>;
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managed = "in-band-status";
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};
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port@8 {
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reg = <8>;
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phy-mode = "internal";
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ethernet = <&enet0>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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port@9 {
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reg = <9>;
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phy-mode = "internal";
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ethernet = <&enet1>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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@ -1,213 +0,0 @@
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Microchip Ocelot switch driver family
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=====================================
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Felix
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-----
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Currently the switches supported by the felix driver are:
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- VSC9959 (Felix)
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- VSC9953 (Seville)
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The VSC9959 switch is found in the NXP LS1028A. It is a PCI device, part of the
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larger ENETC root complex. As a result, the ethernet-switch node is a sub-node
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of the PCIe root complex node and its "reg" property conforms to the parent
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node bindings:
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* reg: Specifies PCIe Device Number and Function Number of the endpoint device,
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in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
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It does not require a "compatible" string.
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The interrupt line is used to signal availability of PTP TX timestamps and for
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TSN frame preemption.
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For the external switch ports, depending on board configuration, "phy-mode" and
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"phy-handle" are populated by board specific device tree instances. Ports 4 and
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5 are fixed as internal ports in the NXP LS1028A instantiation.
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The CPU port property ("ethernet") configures the feature called "NPI port" in
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the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are
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connected, in the Node Processor Interface (NPI) mode, to an Ethernet port.
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By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal
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2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific
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use case. Moving the NPI port to an external switch port is hardware possible,
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but there is no platform support for the Linux system on the LS1028A chip to
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operate as an entire slave DSA chip. NPI functionality (and therefore DSA
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tagging) is supported on a single port at a time.
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Any port can be disabled (and in fsl-ls1028a.dtsi, they are indeed all disabled
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by default, and should be enabled on a per-board basis). But if any external
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switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as
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well, regardless of whether it is configured as the DSA master or not. This is
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because the Felix PHYLINK implementation accesses the MAC PCS registers, which
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in hardware truly belong to the ENETC port #2 and not to Felix.
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Supported PHY interface types (appropriate SerDes protocol setting changes are
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needed in the RCW binary):
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* phy_mode = "internal": on ports 4 and 5
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* phy_mode = "sgmii": on ports 0, 1, 2, 3
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* phy_mode = "qsgmii": on ports 0, 1, 2, 3
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* phy_mode = "usxgmii": on ports 0, 1, 2, 3
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* phy_mode = "2500base-x": on ports 0, 1, 2, 3
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For the rest of the device tree binding definitions, which are standard DSA and
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PCI, refer to the following documents:
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Documentation/devicetree/bindings/net/dsa/dsa.txt
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Documentation/devicetree/bindings/pci/pci.txt
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Example:
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&soc {
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pcie@1f0000000 { /* Integrated Endpoint Root Complex */
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ethernet-switch@0,5 {
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reg = <0x000500 0 0 0 0>;
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/* IEP INT_B */
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* External ports */
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port@0 {
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reg = <0>;
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label = "swp0";
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};
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port@1 {
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reg = <1>;
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label = "swp1";
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};
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port@2 {
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reg = <2>;
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label = "swp2";
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};
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port@3 {
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reg = <3>;
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label = "swp3";
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};
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/* Tagging CPU port */
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port@4 {
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reg = <4>;
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ethernet = <&enetc_port2>;
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phy-mode = "internal";
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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/* Non-tagging CPU port */
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port@5 {
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reg = <5>;
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phy-mode = "internal";
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status = "disabled";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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};
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The VSC9953 switch is found inside NXP T1040. It is a platform device with the
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following required properties:
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- compatible:
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Must be "mscc,vsc9953-switch".
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Supported PHY interface types (appropriate SerDes protocol setting changes are
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needed in the RCW binary):
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* phy_mode = "internal": on ports 8 and 9
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* phy_mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
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* phy_mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
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Example:
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&soc {
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ethernet-switch@800000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "mscc,vsc9953-switch";
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little-endian;
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reg = <0x800000 0x290000>;
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ports {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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port@0 {
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reg = <0x0>;
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label = "swp0";
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};
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port@1 {
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reg = <0x1>;
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label = "swp1";
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};
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port@2 {
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reg = <0x2>;
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label = "swp2";
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};
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port@3 {
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reg = <0x3>;
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label = "swp3";
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};
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port@4 {
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reg = <0x4>;
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label = "swp4";
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};
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port@5 {
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reg = <0x5>;
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label = "swp5";
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};
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port@6 {
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reg = <0x6>;
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label = "swp6";
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};
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port@7 {
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reg = <0x7>;
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label = "swp7";
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};
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port@8 {
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reg = <0x8>;
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phy-mode = "internal";
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ethernet = <&enet0>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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port@9 {
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reg = <0x9>;
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phy-mode = "internal";
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status = "disabled";
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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};
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};
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};
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