forked from Minki/linux
cxgb4: Firmware macro changes for fw verison 1.13.32.0
Adds new macro and few macro changes for fw version 1.13.32.0 also changes version string in driver to match 1.13.32.0 Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -101,7 +101,7 @@ enum fw_wr_opcodes {
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FW_RI_BIND_MW_WR = 0x18,
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FW_RI_FR_NSMR_WR = 0x19,
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FW_RI_INV_LSTAG_WR = 0x1a,
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FW_LASTC2E_WR = 0x40
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FW_LASTC2E_WR = 0x70
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};
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struct fw_wr_hdr {
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@ -993,6 +993,7 @@ enum fw_memtype_cf {
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FW_MEMTYPE_CF_EXTMEM = 0x2,
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FW_MEMTYPE_CF_FLASH = 0x4,
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FW_MEMTYPE_CF_INTERNAL = 0x5,
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FW_MEMTYPE_CF_EXTMEM1 = 0x6,
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};
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struct fw_caps_config_cmd {
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@ -1035,6 +1036,7 @@ enum fw_params_mnem {
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FW_PARAMS_MNEM_PFVF = 2, /* function params */
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FW_PARAMS_MNEM_REG = 3, /* limited register access */
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FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
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FW_PARAMS_MNEM_CHNET = 5, /* chnet params */
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FW_PARAMS_MNEM_LAST
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};
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@ -3102,7 +3104,8 @@ enum fw_devlog_facility {
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FW_DEVLOG_FACILITY_FCOE = 0x2E,
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FW_DEVLOG_FACILITY_FOISCSI = 0x30,
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FW_DEVLOG_FACILITY_FOFCOE = 0x32,
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FW_DEVLOG_FACILITY_MAX = 0x32,
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FW_DEVLOG_FACILITY_CHNET = 0x34,
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FW_DEVLOG_FACILITY_MAX = 0x34,
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};
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/* log message format */
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@ -3139,4 +3142,36 @@ struct fw_devlog_cmd {
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(((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
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FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
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/* P C I E F W P F 7 R E G I S T E R */
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/* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
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* access the "devlog" which needing to contact firmware. The encoding is
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* mostly the same as that returned by the DEVLOG command except for the size
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* which is encoded as the number of entries in multiples-1 of 128 here rather
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* than the memory size as is done in the DEVLOG command. Thus, 0 means 128
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* and 15 means 2048. This of course in turn constrains the allowed values
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* for the devlog size ...
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*/
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#define PCIE_FW_PF_DEVLOG 7
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#define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
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#define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
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#define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
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((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
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#define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
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(((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
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PCIE_FW_PF_DEVLOG_NENTRIES128_M)
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#define PCIE_FW_PF_DEVLOG_ADDR16_S 4
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#define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff
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#define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
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#define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
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(((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
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#define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0
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#define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf
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#define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
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#define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
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(((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
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#endif /* _T4FW_INTERFACE_H_ */
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@ -36,13 +36,13 @@
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#define __T4FW_VERSION_H__
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#define T4FW_VERSION_MAJOR 0x01
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#define T4FW_VERSION_MINOR 0x0C
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#define T4FW_VERSION_MICRO 0x19
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#define T4FW_VERSION_MINOR 0x0D
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#define T4FW_VERSION_MICRO 0x20
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#define T4FW_VERSION_BUILD 0x00
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#define T5FW_VERSION_MAJOR 0x01
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#define T5FW_VERSION_MINOR 0x0C
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#define T5FW_VERSION_MICRO 0x19
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#define T5FW_VERSION_MINOR 0x0D
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#define T5FW_VERSION_MICRO 0x20
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#define T5FW_VERSION_BUILD 0x00
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#endif
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