forked from Minki/linux
mtd: nand: mediatek: add support for different MTK NAND FLASH Controller IP
ECC strength and spare size supported may be different among MTK NAND FLASH Controller IPs. This patch contains changes as following: (1) add new struct mtk_nfc_caps to support different spare size. (2) add new struct mtk_ecc_caps to support different ecc strength. (3) remove ECC_CNFG_xBIT define, use a for loop to do ecc strength config. (4) remove PAGEFMT_SPARE_ define, use a for loop to do spare format config. (5) malloc ecc->eccdata buffer according to max ecc strength of this IP. Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Xiaolei Li
Boris Brezillon
parent
582212ceb9
commit
7ec4a37c5d
@ -33,26 +33,6 @@
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#define ECC_ENCCON (0x00)
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#define ECC_ENCCNFG (0x04)
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#define ECC_CNFG_4BIT (0)
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#define ECC_CNFG_6BIT (1)
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#define ECC_CNFG_8BIT (2)
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#define ECC_CNFG_10BIT (3)
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#define ECC_CNFG_12BIT (4)
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#define ECC_CNFG_14BIT (5)
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#define ECC_CNFG_16BIT (6)
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#define ECC_CNFG_18BIT (7)
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#define ECC_CNFG_20BIT (8)
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#define ECC_CNFG_22BIT (9)
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#define ECC_CNFG_24BIT (0xa)
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#define ECC_CNFG_28BIT (0xb)
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#define ECC_CNFG_32BIT (0xc)
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#define ECC_CNFG_36BIT (0xd)
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#define ECC_CNFG_40BIT (0xe)
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#define ECC_CNFG_44BIT (0xf)
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#define ECC_CNFG_48BIT (0x10)
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#define ECC_CNFG_52BIT (0x11)
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#define ECC_CNFG_56BIT (0x12)
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#define ECC_CNFG_60BIT (0x13)
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#define ECC_MODE_SHIFT (5)
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#define ECC_MS_SHIFT (16)
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#define ECC_ENCDIADDR (0x08)
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@ -66,7 +46,6 @@
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#define DEC_CNFG_CORRECT (0x3 << 12)
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#define ECC_DECIDLE (0x10C)
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#define ECC_DECENUM0 (0x114)
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#define ERR_MASK (0x3f)
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#define ECC_DECDONE (0x124)
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#define ECC_DECIRQ_EN (0x200)
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#define ECC_DECIRQ_STA (0x204)
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@ -78,8 +57,15 @@
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#define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \
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ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
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struct mtk_ecc_caps {
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u32 err_mask;
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const u8 *ecc_strength;
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u8 num_ecc_strength;
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};
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struct mtk_ecc {
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struct device *dev;
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const struct mtk_ecc_caps *caps;
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void __iomem *regs;
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struct clk *clk;
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@ -87,7 +73,13 @@ struct mtk_ecc {
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struct mutex lock;
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u32 sectors;
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u8 eccdata[112];
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u8 *eccdata;
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};
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/* ecc strength that mt2701 supports */
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static const u8 ecc_strength_mt2701[] = {
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4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
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40, 44, 48, 52, 56, 60
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};
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static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
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@ -136,77 +128,24 @@ static irqreturn_t mtk_ecc_irq(int irq, void *id)
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return IRQ_HANDLED;
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}
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static void mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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{
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u32 ecc_bit = ECC_CNFG_4BIT, dec_sz, enc_sz;
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u32 reg;
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u32 ecc_bit, dec_sz, enc_sz;
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u32 reg, i;
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switch (config->strength) {
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case 4:
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ecc_bit = ECC_CNFG_4BIT;
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for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
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if (ecc->caps->ecc_strength[i] == config->strength)
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break;
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case 6:
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ecc_bit = ECC_CNFG_6BIT;
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break;
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case 8:
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ecc_bit = ECC_CNFG_8BIT;
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break;
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case 10:
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ecc_bit = ECC_CNFG_10BIT;
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break;
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case 12:
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ecc_bit = ECC_CNFG_12BIT;
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break;
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case 14:
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ecc_bit = ECC_CNFG_14BIT;
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break;
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case 16:
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ecc_bit = ECC_CNFG_16BIT;
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break;
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case 18:
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ecc_bit = ECC_CNFG_18BIT;
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break;
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case 20:
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ecc_bit = ECC_CNFG_20BIT;
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break;
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case 22:
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ecc_bit = ECC_CNFG_22BIT;
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break;
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case 24:
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ecc_bit = ECC_CNFG_24BIT;
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break;
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case 28:
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ecc_bit = ECC_CNFG_28BIT;
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break;
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case 32:
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ecc_bit = ECC_CNFG_32BIT;
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break;
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case 36:
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ecc_bit = ECC_CNFG_36BIT;
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break;
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case 40:
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ecc_bit = ECC_CNFG_40BIT;
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break;
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case 44:
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ecc_bit = ECC_CNFG_44BIT;
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break;
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case 48:
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ecc_bit = ECC_CNFG_48BIT;
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break;
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case 52:
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ecc_bit = ECC_CNFG_52BIT;
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break;
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case 56:
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ecc_bit = ECC_CNFG_56BIT;
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break;
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case 60:
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ecc_bit = ECC_CNFG_60BIT;
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break;
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default:
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dev_err(ecc->dev, "invalid strength %d, default to 4 bits\n",
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config->strength);
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}
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if (i == ecc->caps->num_ecc_strength) {
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dev_err(ecc->dev, "invalid ecc strength %d\n",
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config->strength);
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return -EINVAL;
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}
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ecc_bit = i;
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if (config->op == ECC_ENCODE) {
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/* configure ECC encoder (in bits) */
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enc_sz = config->len << 3;
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@ -232,6 +171,8 @@ static void mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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if (config->sectors)
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ecc->sectors = 1 << (config->sectors - 1);
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}
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return 0;
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}
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void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
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@ -247,8 +188,8 @@ void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
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offset = (i >> 2) << 2;
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err = readl(ecc->regs + ECC_DECENUM0 + offset);
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err = err >> ((i % 4) * 8);
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err &= ERR_MASK;
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if (err == ERR_MASK) {
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err &= ecc->caps->err_mask;
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if (err == ecc->caps->err_mask) {
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/* uncorrectable errors */
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stats->failed++;
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continue;
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@ -322,7 +263,11 @@ int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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}
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mtk_ecc_wait_idle(ecc, op);
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mtk_ecc_config(ecc, config);
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ret = mtk_ecc_config(ecc, config);
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if (ret)
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return ret;
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writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
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init_completion(&ecc->done);
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@ -409,37 +354,66 @@ timeout:
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}
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EXPORT_SYMBOL(mtk_ecc_encode);
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void mtk_ecc_adjust_strength(u32 *p)
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void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
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{
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u32 ecc[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
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40, 44, 48, 52, 56, 60};
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const u8 *ecc_strength = ecc->caps->ecc_strength;
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int i;
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for (i = 0; i < ARRAY_SIZE(ecc); i++) {
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if (*p <= ecc[i]) {
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for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
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if (*p <= ecc_strength[i]) {
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if (!i)
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*p = ecc[i];
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else if (*p != ecc[i])
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*p = ecc[i - 1];
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*p = ecc_strength[i];
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else if (*p != ecc_strength[i])
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*p = ecc_strength[i - 1];
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return;
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}
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}
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*p = ecc[ARRAY_SIZE(ecc) - 1];
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*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
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}
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EXPORT_SYMBOL(mtk_ecc_adjust_strength);
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static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
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.err_mask = 0x3f,
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.ecc_strength = ecc_strength_mt2701,
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.num_ecc_strength = 20,
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};
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static const struct of_device_id mtk_ecc_dt_match[] = {
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{
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.compatible = "mediatek,mt2701-ecc",
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.data = &mtk_ecc_caps_mt2701,
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},
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{},
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};
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static int mtk_ecc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_ecc *ecc;
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struct resource *res;
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const struct of_device_id *of_ecc_id = NULL;
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u32 max_eccdata_size;
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int irq, ret;
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ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
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if (!ecc)
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return -ENOMEM;
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of_ecc_id = of_match_device(mtk_ecc_dt_match, &pdev->dev);
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if (!of_ecc_id)
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return -ENODEV;
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ecc->caps = of_ecc_id->data;
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max_eccdata_size = ecc->caps->num_ecc_strength - 1;
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max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
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max_eccdata_size = (max_eccdata_size * ECC_PARITY_BITS + 7) >> 3;
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max_eccdata_size = round_up(max_eccdata_size, 4);
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ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
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if (!ecc->eccdata)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ecc->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(ecc->regs)) {
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@ -508,11 +482,6 @@ static int mtk_ecc_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
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#endif
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static const struct of_device_id mtk_ecc_dt_match[] = {
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{ .compatible = "mediatek,mt2701-ecc" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
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static struct platform_driver mtk_ecc_driver = {
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@ -42,7 +42,7 @@ void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
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int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
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int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
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void mtk_ecc_disable(struct mtk_ecc *);
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void mtk_ecc_adjust_strength(u32 *);
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void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
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struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
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void mtk_ecc_release(struct mtk_ecc *);
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@ -24,6 +24,7 @@
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#include <linux/module.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "mtk_ecc.h"
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/* NAND controller register definition */
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@ -38,23 +39,6 @@
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#define NFI_PAGEFMT (0x04)
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#define PAGEFMT_FDM_ECC_SHIFT (12)
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#define PAGEFMT_FDM_SHIFT (8)
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#define PAGEFMT_SPARE_16 (0)
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#define PAGEFMT_SPARE_26 (1)
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#define PAGEFMT_SPARE_27 (2)
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#define PAGEFMT_SPARE_28 (3)
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#define PAGEFMT_SPARE_32 (4)
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#define PAGEFMT_SPARE_36 (5)
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#define PAGEFMT_SPARE_40 (6)
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#define PAGEFMT_SPARE_44 (7)
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#define PAGEFMT_SPARE_48 (8)
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#define PAGEFMT_SPARE_49 (9)
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#define PAGEFMT_SPARE_50 (0xa)
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#define PAGEFMT_SPARE_51 (0xb)
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#define PAGEFMT_SPARE_52 (0xc)
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#define PAGEFMT_SPARE_62 (0xd)
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#define PAGEFMT_SPARE_63 (0xe)
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#define PAGEFMT_SPARE_64 (0xf)
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#define PAGEFMT_SPARE_SHIFT (4)
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#define PAGEFMT_SEC_SEL_512 BIT(2)
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#define PAGEFMT_512_2K (0)
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#define PAGEFMT_2K_4K (1)
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@ -115,6 +99,13 @@
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#define MTK_RESET_TIMEOUT (1000000)
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#define MTK_MAX_SECTOR (16)
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#define MTK_NAND_MAX_NSELS (2)
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#define MTK_NFC_MIN_SPARE (16)
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struct mtk_nfc_caps {
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const u8 *spare_size;
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u8 num_spare_size;
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u8 pageformat_spare_shift;
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};
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struct mtk_nfc_bad_mark_ctl {
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void (*bm_swap)(struct mtd_info *, u8 *buf, int raw);
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@ -155,6 +146,7 @@ struct mtk_nfc {
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struct mtk_ecc *ecc;
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struct device *dev;
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const struct mtk_nfc_caps *caps;
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void __iomem *regs;
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struct completion done;
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@ -163,6 +155,15 @@ struct mtk_nfc {
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u8 *buffer;
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};
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/*
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* supported spare size of each IP.
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* order should be the same with the spare size bitfiled defination of
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* register NFI_PAGEFMT.
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*/
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static const u8 spare_size_mt2701[] = {
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16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64
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};
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static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
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{
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return container_of(nand, struct mtk_nfc_nand_chip, nand);
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@ -308,7 +309,7 @@ static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
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struct mtk_nfc *nfc = nand_get_controller_data(chip);
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u32 fmt, spare;
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u32 fmt, spare, i;
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if (!mtd->writesize)
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return 0;
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@ -352,60 +353,18 @@ static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
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if (chip->ecc.size == 1024)
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spare >>= 1;
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switch (spare) {
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case 16:
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fmt |= (PAGEFMT_SPARE_16 << PAGEFMT_SPARE_SHIFT);
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for (i = 0; i < nfc->caps->num_spare_size; i++) {
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if (nfc->caps->spare_size[i] == spare)
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break;
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case 26:
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fmt |= (PAGEFMT_SPARE_26 << PAGEFMT_SPARE_SHIFT);
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break;
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case 27:
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fmt |= (PAGEFMT_SPARE_27 << PAGEFMT_SPARE_SHIFT);
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break;
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case 28:
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fmt |= (PAGEFMT_SPARE_28 << PAGEFMT_SPARE_SHIFT);
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break;
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case 32:
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fmt |= (PAGEFMT_SPARE_32 << PAGEFMT_SPARE_SHIFT);
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break;
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case 36:
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fmt |= (PAGEFMT_SPARE_36 << PAGEFMT_SPARE_SHIFT);
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break;
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case 40:
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fmt |= (PAGEFMT_SPARE_40 << PAGEFMT_SPARE_SHIFT);
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break;
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case 44:
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fmt |= (PAGEFMT_SPARE_44 << PAGEFMT_SPARE_SHIFT);
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break;
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case 48:
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fmt |= (PAGEFMT_SPARE_48 << PAGEFMT_SPARE_SHIFT);
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break;
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case 49:
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fmt |= (PAGEFMT_SPARE_49 << PAGEFMT_SPARE_SHIFT);
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break;
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case 50:
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fmt |= (PAGEFMT_SPARE_50 << PAGEFMT_SPARE_SHIFT);
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break;
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case 51:
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fmt |= (PAGEFMT_SPARE_51 << PAGEFMT_SPARE_SHIFT);
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break;
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case 52:
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fmt |= (PAGEFMT_SPARE_52 << PAGEFMT_SPARE_SHIFT);
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break;
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case 62:
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fmt |= (PAGEFMT_SPARE_62 << PAGEFMT_SPARE_SHIFT);
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break;
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case 63:
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fmt |= (PAGEFMT_SPARE_63 << PAGEFMT_SPARE_SHIFT);
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break;
|
||||
case 64:
|
||||
fmt |= (PAGEFMT_SPARE_64 << PAGEFMT_SPARE_SHIFT);
|
||||
break;
|
||||
default:
|
||||
dev_err(nfc->dev, "invalid spare per sector %d\n", spare);
|
||||
}
|
||||
|
||||
if (i == nfc->caps->num_spare_size) {
|
||||
dev_err(nfc->dev, "invalid spare size %d\n", spare);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fmt |= i << nfc->caps->pageformat_spare_shift;
|
||||
|
||||
fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT;
|
||||
fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT;
|
||||
nfi_writel(nfc, fmt, NFI_PAGEFMT);
|
||||
@ -1131,12 +1090,12 @@ static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
|
||||
}
|
||||
}
|
||||
|
||||
static void mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
|
||||
static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *nand = mtd_to_nand(mtd);
|
||||
u32 spare[] = {16, 26, 27, 28, 32, 36, 40, 44,
|
||||
48, 49, 50, 51, 52, 62, 63, 64};
|
||||
u32 eccsteps, i;
|
||||
struct mtk_nfc *nfc = nand_get_controller_data(nand);
|
||||
const u8 *spare = nfc->caps->spare_size;
|
||||
u32 eccsteps, i, closest_spare = 0;
|
||||
|
||||
eccsteps = mtd->writesize / nand->ecc.size;
|
||||
*sps = mtd->oobsize / eccsteps;
|
||||
@ -1144,28 +1103,31 @@ static void mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
|
||||
if (nand->ecc.size == 1024)
|
||||
*sps >>= 1;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(spare); i++) {
|
||||
if (*sps <= spare[i]) {
|
||||
if (!i)
|
||||
*sps = spare[i];
|
||||
else if (*sps != spare[i])
|
||||
*sps = spare[i - 1];
|
||||
if (*sps < MTK_NFC_MIN_SPARE)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < nfc->caps->num_spare_size; i++) {
|
||||
if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) {
|
||||
closest_spare = i;
|
||||
if (*sps == spare[i])
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i >= ARRAY_SIZE(spare))
|
||||
*sps = spare[ARRAY_SIZE(spare) - 1];
|
||||
*sps = spare[closest_spare];
|
||||
|
||||
if (nand->ecc.size == 1024)
|
||||
*sps <<= 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *nand = mtd_to_nand(mtd);
|
||||
struct mtk_nfc *nfc = nand_get_controller_data(nand);
|
||||
u32 spare;
|
||||
int free;
|
||||
int free, ret;
|
||||
|
||||
/* support only ecc hw mode */
|
||||
if (nand->ecc.mode != NAND_ECC_HW) {
|
||||
@ -1194,7 +1156,9 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
|
||||
nand->ecc.size = 1024;
|
||||
}
|
||||
|
||||
mtk_nfc_set_spare_per_sector(&spare, mtd);
|
||||
ret = mtk_nfc_set_spare_per_sector(&spare, mtd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* calculate oob bytes except ecc parity data */
|
||||
free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3;
|
||||
@ -1214,7 +1178,7 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
|
||||
}
|
||||
}
|
||||
|
||||
mtk_ecc_adjust_strength(&nand->ecc.strength);
|
||||
mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength);
|
||||
|
||||
dev_info(dev, "eccsize %d eccstrength %d\n",
|
||||
nand->ecc.size, nand->ecc.strength);
|
||||
@ -1312,7 +1276,10 @@ static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, mtd);
|
||||
ret = mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, mtd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mtk_nfc_set_fdm(&chip->fdm, mtd);
|
||||
mtk_nfc_set_bad_mark_ctl(&chip->bad_mark, mtd);
|
||||
|
||||
@ -1354,12 +1321,28 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
|
||||
.spare_size = spare_size_mt2701,
|
||||
.num_spare_size = 16,
|
||||
.pageformat_spare_shift = 4,
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_nfc_id_table[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt2701-nfc",
|
||||
.data = &mtk_nfc_caps_mt2701,
|
||||
},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
|
||||
|
||||
static int mtk_nfc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct mtk_nfc *nfc;
|
||||
struct resource *res;
|
||||
const struct of_device_id *of_nfc_id = NULL;
|
||||
int ret, irq;
|
||||
|
||||
nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
|
||||
@ -1423,6 +1406,14 @@ static int mtk_nfc_probe(struct platform_device *pdev)
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
of_nfc_id = of_match_device(mtk_nfc_id_table, &pdev->dev);
|
||||
if (!of_nfc_id) {
|
||||
ret = -ENODEV;
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
nfc->caps = of_nfc_id->data;
|
||||
|
||||
platform_set_drvdata(pdev, nfc);
|
||||
|
||||
ret = mtk_nfc_nand_chips_init(dev, nfc);
|
||||
@ -1503,12 +1494,6 @@ static int mtk_nfc_resume(struct device *dev)
|
||||
static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
|
||||
#endif
|
||||
|
||||
static const struct of_device_id mtk_nfc_id_table[] = {
|
||||
{ .compatible = "mediatek,mt2701-nfc" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
|
||||
|
||||
static struct platform_driver mtk_nfc_driver = {
|
||||
.probe = mtk_nfc_probe,
|
||||
.remove = mtk_nfc_remove,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user