forked from Minki/linux
ptp: ptp_clockmatrix: update to support 4.8.7 firmware
With 4.8.7 firmware, adjtime can change delta instead of absolute time, which greately increases snap accuracy. PPS alignment doesn't have to be set for every single TOD change. Other minor changes includes: adding more debug logs, increasing snap accuracy for pre 4.8.7 firmware and supporting new tcs2bin format. Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Min Li
David S. Miller
parent
2a043e9cec
commit
7ea5fda2b1
@ -20,6 +20,10 @@
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#define HW_DPLL_1 (0x8b00)
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#define HW_DPLL_2 (0x8c00)
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#define HW_DPLL_3 (0x8d00)
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#define HW_DPLL_4 (0x8e00)
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#define HW_DPLL_5 (0x8f00)
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#define HW_DPLL_6 (0x9000)
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#define HW_DPLL_7 (0x9100)
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#define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
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#define HW_DPLL_TOD_CTRL_1 (0x089)
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@ -57,6 +61,43 @@
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#define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
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#define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
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#define HW_Q8_CTRL_SPARE (0xa7d4)
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#define HW_Q11_CTRL_SPARE (0xa7ec)
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/**
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* Select FOD5 as sync_trigger for Q8 divider.
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* Transition from logic zero to one
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* sets trigger to sync Q8 divider.
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*
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* Unused when FOD4 is driving Q8 divider (normal operation).
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*/
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#define Q9_TO_Q8_SYNC_TRIG BIT(1)
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/**
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* Enable FOD5 as driver for clock and sync for Q8 divider.
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* Enable fanout buffer for FOD5.
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*
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* Unused when FOD4 is driving Q8 divider (normal operation).
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*/
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#define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
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/**
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* Select FOD6 as sync_trigger for Q11 divider.
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* Transition from logic zero to one
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* sets trigger to sync Q11 divider.
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*
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* Unused when FOD7 is driving Q11 divider (normal operation).
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*/
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#define Q10_TO_Q11_SYNC_TRIG BIT(1)
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/**
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* Enable FOD6 as driver for clock and sync for Q11 divider.
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* Enable fanout buffer for FOD6.
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*
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* Unused when FOD7 is driving Q11 divider (normal operation).
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*/
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#define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
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#define RESET_CTRL 0xc000
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#define SM_RESET 0x0012
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#define SM_RESET_CMD 0x5A
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@ -191,6 +232,7 @@
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#define DPLL_CTRL_0 0xc600
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#define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
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#define DPLL_CTRL_COMBO_MASTER_CFG 0x003a
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#define DPLL_CTRL_1 0xc63c
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@ -646,6 +688,9 @@
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/* Bit definitions for the TOD_WRITE_CMD register */
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#define TOD_WRITE_SELECTION_SHIFT (0)
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#define TOD_WRITE_SELECTION_MASK (0xf)
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/* 4.8.7 */
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#define TOD_WRITE_TYPE_SHIFT (4)
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#define TOD_WRITE_TYPE_MASK (0x3)
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/* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
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#define RD_PWM_DECODER_INDEX_SHIFT (4)
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@ -658,4 +703,7 @@
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#define TOD_READ_TRIGGER_SHIFT (0)
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#define TOD_READ_TRIGGER_MASK (0xf)
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/* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
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#define COMBO_MASTER_HOLD BIT(0)
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#endif
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File diff suppressed because it is too large
Load Diff
@ -13,32 +13,48 @@
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#include "idt8a340_reg.h"
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#define FW_FILENAME "idtcm.bin"
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#define MAX_PHC_PLL 4
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#define MAX_TOD (4)
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#define MAX_PLL (8)
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#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
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#define PLL_MASK_ADDR (0xFFA5)
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#define DEFAULT_PLL_MASK (0x04)
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#define TOD_MASK_ADDR (0xFFA5)
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#define DEFAULT_TOD_MASK (0x04)
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#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
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#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
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#define OUTPUT_MASK_PLL0_ADDR (0xFFB0)
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#define OUTPUT_MASK_PLL1_ADDR (0xFFB2)
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#define OUTPUT_MASK_PLL2_ADDR (0xFFB4)
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#define OUTPUT_MASK_PLL3_ADDR (0xFFB6)
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#define TOD0_PTP_PLL_ADDR (0xFFA8)
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#define TOD1_PTP_PLL_ADDR (0xFFA9)
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#define TOD2_PTP_PLL_ADDR (0xFFAA)
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#define TOD3_PTP_PLL_ADDR (0xFFAB)
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#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0)
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#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2)
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#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4)
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#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6)
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#define DEFAULT_OUTPUT_MASK_PLL0 (0x003)
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#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c)
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#define DEFAULT_OUTPUT_MASK_PLL2 (0x030)
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#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0)
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#define DEFAULT_TOD0_PTP_PLL (0)
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#define DEFAULT_TOD1_PTP_PLL (1)
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#define DEFAULT_TOD2_PTP_PLL (2)
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#define DEFAULT_TOD3_PTP_PLL (3)
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#define POST_SM_RESET_DELAY_MS (3000)
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#define PHASE_PULL_IN_THRESHOLD_NS (150000)
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#define TOD_WRITE_OVERHEAD_COUNT_MAX (5)
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#define PHASE_PULL_IN_THRESHOLD_NS_V487 (15000)
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#define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
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#define TOD_BYTE_COUNT (11)
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#define WR_PHASE_SETUP_MS (5000)
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#define OUTPUT_MODULE_FROM_INDEX(index) (OUTPUT_0 + (index) * 0x10)
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#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
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/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
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enum pll_mode {
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PLL_MODE_MIN = 0,
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@ -48,7 +64,8 @@ enum pll_mode {
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PLL_MODE_GPIO_INC_DEC = 3,
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PLL_MODE_SYNTHESIS = 4,
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PLL_MODE_PHASE_MEASUREMENT = 5,
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PLL_MODE_MAX = PLL_MODE_PHASE_MEASUREMENT,
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PLL_MODE_DISABLED = 6,
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PLL_MODE_MAX = PLL_MODE_DISABLED,
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};
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enum hw_tod_write_trig_sel {
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@ -63,6 +80,26 @@ enum hw_tod_write_trig_sel {
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WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
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};
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/* 4.8.7 only */
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enum scsr_tod_write_trig_sel {
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SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
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SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
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SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
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SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
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SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
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SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
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SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
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SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
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};
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/* 4.8.7 only */
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enum scsr_tod_write_type_sel {
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SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
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SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
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SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
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SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
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};
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struct idtcm;
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struct idtcm_channel {
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@ -79,15 +116,17 @@ struct idtcm_channel {
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u16 tod_n;
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u16 hw_dpll_n;
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enum pll_mode pll_mode;
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u8 pll;
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u16 output_mask;
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int write_phase_ready;
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};
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struct idtcm {
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struct idtcm_channel channel[MAX_PHC_PLL];
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struct idtcm_channel channel[MAX_TOD];
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struct i2c_client *client;
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u8 page_offset;
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u8 pll_mask;
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u8 tod_mask;
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char version[16];
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/* Overhead calculation for adjtime */
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u8 calculate_overhead_flag;
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