forked from Minki/linux
ARM: mach-shmobile: intc-sh7377: Add INTCS support
Add support for the sh7377 INTCS interrupt controller. INTCS is the interrupt controller for the sh7377 SuperH processor core. It is tied into the INTCA interrupt controller which interfaces to the ARM processor. INTCS support is implemented using a new INTC table together with a chained interrupt handler that ties into the already supported INTCA controller. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Kuninori Morimoto
Paul Mundt
parent
0e9131a3fa
commit
7da5c86883
@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = {
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intca_sense_registers, intca_ack_registers),
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};
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/* this macro ignore entry which is also in INTCA */
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#define __IGNORE(a...)
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#define __IGNORE0(a...) 0
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enum {
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UNUSED_INTCS = 0,
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INTCS,
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/* interrupt sources INTCS */
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VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
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RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
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CEU,
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BEU_BEU0, BEU_BEU1, BEU_BEU2,
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__IGNORE(MFI)
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__IGNORE(BBIF2)
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VPU,
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TSIF1,
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__IGNORE(SGX540)
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_2DDMAC,
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IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
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IPMMU_IPMMUR, IPMMU_IPMMUR2,
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RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
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__IGNORE(KEYSC)
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__IGNORE(TTI20)
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__IGNORE(MSIOF)
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IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
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TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
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CMT0,
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TSIF0,
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__IGNORE(CMT2)
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LMB,
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__IGNORE(MSUG)
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__IGNORE(MSU_MSU, MSU_MSU2)
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__IGNORE(CTI)
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MVI3,
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__IGNORE(RWDT0)
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__IGNORE(RWDT1)
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ICB,
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PEP,
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ASA,
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__IGNORE(_2DG)
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HQE,
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JPU,
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LCDC0,
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__IGNORE(LCRC)
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RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
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RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
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FRC,
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LCDC1,
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CSIRX,
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DSITX_DSITX0, DSITX_DSITX1,
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__IGNORE(SPU2_SPU0, SPU2_SPU1)
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__IGNORE(FSI)
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__IGNORE(FMSI)
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__IGNORE(SCUV)
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TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
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TSIF2,
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CMT4,
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__IGNORE(MFIS2)
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CPORTS2R,
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/* interrupt groups INTCS */
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RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
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IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
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};
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#define INTCS_INTVECT 0x0F80
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static struct intc_vect intcs_vectors[] __initdata = {
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INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
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INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
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INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
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INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
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INTCS_VECT(CEU, 0x0880),
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INTCS_VECT(BEU_BEU0, 0x08A0),
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INTCS_VECT(BEU_BEU1, 0x08C0),
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INTCS_VECT(BEU_BEU2, 0x08E0),
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__IGNORE(INTCS_VECT(MFI, 0x0900))
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__IGNORE(INTCS_VECT(BBIF2, 0x0960))
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INTCS_VECT(VPU, 0x0980),
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INTCS_VECT(TSIF1, 0x09A0),
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__IGNORE(INTCS_VECT(SGX540, 0x09E0))
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INTCS_VECT(_2DDMAC, 0x0A00),
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INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
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INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
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INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
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INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
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INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
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INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
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__IGNORE(INTCS_VECT(KEYSC 0x0BE0))
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__IGNORE(INTCS_VECT(TTI20, 0x0C80))
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__IGNORE(INTCS_VECT(MSIOF, 0x0D20))
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INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
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INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
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INTCS_VECT(TMU_TUNI0, 0x0E80),
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INTCS_VECT(TMU_TUNI1, 0x0EA0),
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INTCS_VECT(TMU_TUNI2, 0x0EC0),
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INTCS_VECT(CMT0, 0x0F00),
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INTCS_VECT(TSIF0, 0x0F20),
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__IGNORE(INTCS_VECT(CMT2, 0x0F40))
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INTCS_VECT(LMB, 0x0F60),
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__IGNORE(INTCS_VECT(MSUG, 0x0F80))
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__IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
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__IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
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__IGNORE(INTCS_VECT(CTI, 0x0400))
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INTCS_VECT(MVI3, 0x0420),
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__IGNORE(INTCS_VECT(RWDT0, 0x0440))
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__IGNORE(INTCS_VECT(RWDT1, 0x0460))
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INTCS_VECT(ICB, 0x0480),
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INTCS_VECT(PEP, 0x04A0),
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INTCS_VECT(ASA, 0x04C0),
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__IGNORE(INTCS_VECT(_2DG, 0x04E0))
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INTCS_VECT(HQE, 0x0540),
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INTCS_VECT(JPU, 0x0560),
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INTCS_VECT(LCDC0, 0x0580),
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__IGNORE(INTCS_VECT(LCRC, 0x05A0))
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INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
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INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
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INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
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INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
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INTCS_VECT(FRC, 0x1700),
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INTCS_VECT(LCDC1, 0x1780),
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INTCS_VECT(CSIRX, 0x17A0),
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INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
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__IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
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__IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
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__IGNORE(INTCS_VECT(FSI, 0x1840))
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__IGNORE(INTCS_VECT(FMSI, 0x1860))
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__IGNORE(INTCS_VECT(SCUV, 0x1880))
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INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
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INTCS_VECT(TMU1_TUNI12, 0x1940),
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INTCS_VECT(TSIF2, 0x1960),
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INTCS_VECT(CMT4, 0x1980),
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__IGNORE(INTCS_VECT(MFIS2, 0x1A00))
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INTCS_VECT(CPORTS2R, 0x1A20),
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INTC_VECT(INTCS, INTCS_INTVECT),
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};
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static struct intc_group intcs_groups[] __initdata = {
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INTC_GROUP(RTDMAC1_1,
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RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
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RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
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INTC_GROUP(RTDMAC1_2,
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RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
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INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
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INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
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INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
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__IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
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INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
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INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
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INTC_GROUP(RTDMAC2_1,
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RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
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RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
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INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
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INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
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__IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
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INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
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};
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static struct intc_mask_reg intcs_mask_registers[] __initdata = {
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{ 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
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{ BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
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VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
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{ 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
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{ 0, 0, 0, VPU,
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__IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
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{ 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
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{ 0, 0, 0, _2DDMAC,
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__IGNORE0(_2DG), ASA, PEP, ICB } },
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{ 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
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{ 0, 0, MVI3, __IGNORE0(CTI),
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JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
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{ 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
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{ __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
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RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
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__IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
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{ 0, 0, MSIOF, 0,
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SGX540, 0, TTI20, 0 } })
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{ 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
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{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
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0, 0, 0, 0 } },
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__IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
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{ 0, 0, 0, 0,
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0, MSU_MSU, MSU_MSU2, MSUG } })
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{ 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
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{ __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
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IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
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{ 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
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{ 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
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0, 0, 0, 0 } },
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{ 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
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{ IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
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0, TSIF1, LMB, TSIF0 } },
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{ 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
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{ RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
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RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
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{ 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
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{ FRC, 0, 0, 0,
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LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
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__IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
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{SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
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SCUV, 0, 0, 0 } })
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{ 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
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{ TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
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CMT4, 0, 0, 0 } },
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{ 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
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{ __IGNORE0(MFIS2), CPORTS2R, 0, 0,
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0, 0, 0, 0 } },
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{ 0xFFD20104, 0, 16, /* INTAMASK */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, INTCS } }
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};
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static struct intc_prio_reg intcs_prio_registers[] __initdata = {
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/* IPRAS */
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{ 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
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/* IPRBS */
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{ 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
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/* IPRCS */
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__IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
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/* IPRES */
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{ 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
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/* IPRFS */
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{ 0xFFD20014, 0, 16, 4,
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{ __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
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/* IPRGS */
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{ 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
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/* IPRHS */
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{ 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
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/* IPRIS */
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{ 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
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/* IPRJS */
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__IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
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/* IPRKS */
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{ 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
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/* IPRLS */
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{ 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
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/* IPRMS */
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{ 0xFFD20030, 0, 16, 4,
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{ IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
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/* IPRAS3 */
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{ 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
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/* IPRBS3 */
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{ 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
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/* IPRIS3 */
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{ 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
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/* IPRJS3 */
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{ 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
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/* IPRKS3 */
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__IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
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/* IPRLS3 */
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__IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
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/* IPRMS3 */
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{ 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
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/* IPRNS3 */
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{ 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
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/* IPROS3 */
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{ 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
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};
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static struct resource intcs_resources[] __initdata = {
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[0] = {
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.start = 0xffd20000,
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.end = 0xffd500ff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct intc_desc intcs_desc __initdata = {
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.name = "sh7377-intcs",
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.resource = intcs_resources,
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.num_resources = ARRAY_SIZE(intcs_resources),
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.hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
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intcs_mask_registers, intcs_prio_registers,
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NULL, NULL),
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};
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static void intcs_demux(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *reg = (void *)get_irq_data(irq);
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unsigned int evtcodeas = ioread32(reg);
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generic_handle_irq(intcs_evt2irq(evtcodeas));
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}
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#define INTEVTSA 0xFFD20100
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void __init sh7377_init_irq(void)
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{
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void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
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register_intc_controller(&intca_desc);
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register_intc_controller(&intcs_desc);
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/* demux using INTEVTSA */
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set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
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set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
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}
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