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drm/amd/pp: Switch the tolerable latency for display

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Select the lowest MCLK frequency that is within
the tolerable latency defined in DISPALY

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
rex zhu 2018-06-28 13:55:46 +08:00 committed by Alex Deucher
parent 6eb9d60304
commit 7d8d968dac
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
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@ -3217,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
/* Find the lowest MCLK frequency that is within
* the tolerable latency defined in DAL
*/
latency = 0;
latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
for (i = 0; i < data->mclk_latency_table.count; i++) {
if ((data->mclk_latency_table.entries[i].latency <= latency) &&
(data->mclk_latency_table.entries[i].frequency >=