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staging: comedi: addi_apci_1564: use addi_tcw.h defines for counters

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Use the generic TCW (timer/counter/watchdog) defines for the 32-bit counters.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2014-11-10 16:20:19 -07:00 committed by Greg Kroah-Hartman
parent e23337dcbb
commit 7d6156ed3b
2 changed files with 34 additions and 36 deletions
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35
drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c
View File

@ -40,12 +40,12 @@ static int apci1564_timer_insn_config(struct comedi_device *dev,
outl(0x0, dev->iobase + APCI1564_DO_IRQ_REG);
outl(0x0, dev->iobase + APCI1564_WDOG_IRQ_REG);
if (devpriv->counters) {
outl(0x0,
devpriv->counters + APCI1564_COUNTER_IRQ_REG(0));
outl(0x0,
devpriv->counters + APCI1564_COUNTER_IRQ_REG(1));
outl(0x0,
devpriv->counters + APCI1564_COUNTER_IRQ_REG(2));
unsigned long iobase;
iobase = devpriv->counters + ADDI_TCW_IRQ_REG;
outl(0x0, iobase + APCI1564_COUNTER(0));
outl(0x0, iobase + APCI1564_COUNTER(1));
outl(0x0, iobase + APCI1564_COUNTER(2));
}
} else {
/* disable Timer interrupt */
@ -113,18 +113,19 @@ static int apci1564_counter_insn_config(struct comedi_device *dev,
{
struct apci1564_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
unsigned int ctrl;
devpriv->tsk_current = current;
/* First Stop The Counter */
ctrl = inl(devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
ctrl &= 0xfffff9fe;
/* Stop The Timer */
outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
/* Set the reload value */
outl(data[3], devpriv->counters + APCI1564_COUNTER_RELOAD_REG(chan));
outl(data[3], iobase + ADDI_TCW_RELOAD_REG);
/* Set the mode : */
/* - Disable the hardware */
@ -136,17 +137,17 @@ static int apci1564_counter_insn_config(struct comedi_device *dev,
ctrl &= 0xfffc19e2;
ctrl |= 0x80000 | (data[4] << 16);
outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
/* Enable or Disable Interrupt */
ctrl &= 0xfffff9fd;
ctrl |= (data[1] << 1);
outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
/* Set the Up/Down selection */
ctrl &= 0xfffbf9ff;
ctrl |= (data[6] << 18);
outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
return insn->n;
}
@ -158,9 +159,10 @@ static int apci1564_counter_insn_write(struct comedi_device *dev,
{
struct apci1564_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
unsigned int ctrl;
ctrl = inl(devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
switch (data[1]) {
case 0: /* Stops the Counter subdevice */
ctrl = 0;
@ -174,7 +176,7 @@ static int apci1564_counter_insn_write(struct comedi_device *dev,
ctrl |= 0x400;
break;
}
outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
return insn->n;
}
@ -186,12 +188,13 @@ static int apci1564_counter_insn_read(struct comedi_device *dev,
{
struct apci1564_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
unsigned int status;
/* Read the Counter Actual Value. */
data[0] = inl(devpriv->counters + APCI1564_COUNTER_REG(chan));
data[0] = inl(iobase + ADDI_TCW_VAL_REG);
status = inl(devpriv->counters + APCI1564_COUNTER_STATUS_REG(chan));
status = inl(iobase + ADDI_TCW_STATUS_REG);
data[1] = (status >> 1) & 1; /* software trigger status */
data[2] = (status >> 2) & 1; /* hardware trigger status */
data[3] = (status >> 3) & 1; /* software clear status */

35
drivers/staging/comedi/drivers/addi_apci_1564.c
View File

@ -101,17 +101,10 @@
*/
/*
* devpriv->counters Register Map
* devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
* PLD Revision 2.x - PCI BAR 1 + 0x00
*/
#define APCI1564_COUNTER_REG(x) (0x00 + ((x) * 0x20))
#define APCI1564_COUNTER_RELOAD_REG(x) (0x04 + ((x) * 0x20))
#define APCI1564_COUNTER_TIMEBASE_REG(x) (0x08 + ((x) * 0x20))
#define APCI1564_COUNTER_CTRL_REG(x) (0x0c + ((x) * 0x20))
#define APCI1564_COUNTER_STATUS_REG(x) (0x10 + ((x) * 0x20))
#define APCI1564_COUNTER_IRQ_REG(x) (0x14 + ((x) * 0x20))
#define APCI1564_COUNTER_WARN_TIMEVAL_REG(x) (0x18 + ((x) * 0x20))
#define APCI1564_COUNTER_WARN_TIMEBASE_REG(x) (0x1c + ((x) * 0x20))
#define APCI1564_COUNTER(x) ((x) * 0x20)
struct apci1564_private {
unsigned long eeprom; /* base address of EEPROM register */
@ -147,10 +140,12 @@ static int apci1564_reset(struct comedi_device *dev)
outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
if (devpriv->counters) {
unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
/* Reset the counter registers */
outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(0));
outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(1));
outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(2));
outl(0x0, iobase + APCI1564_COUNTER(0));
outl(0x0, iobase + APCI1564_COUNTER(1));
outl(0x0, iobase + APCI1564_COUNTER(2));
}
return 0;
@ -195,21 +190,21 @@ static irqreturn_t apci1564_interrupt(int irq, void *d)
if (devpriv->counters) {
for (chan = 0; chan < 4; chan++) {
status = inl(devpriv->counters +
APCI1564_COUNTER_IRQ_REG(chan));
unsigned long iobase;
iobase = devpriv->counters + APCI1564_COUNTER(chan);
status = inl(iobase + ADDI_TCW_IRQ_REG);
if (status & 0x01) {
/* Disable Counter Interrupt */
ctrl = inl(devpriv->counters +
APCI1564_COUNTER_CTRL_REG(chan));
outl(0x0, devpriv->counters +
APCI1564_COUNTER_CTRL_REG(chan));
ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
outl(0x0, iobase + ADDI_TCW_CTRL_REG);
/* Send a signal to from kernel to user space */
send_sig(SIGIO, devpriv->tsk_current, 0);
/* Enable Counter Interrupt */
outl(ctrl, devpriv->counters +
APCI1564_COUNTER_CTRL_REG(chan));
outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
}
}
}