dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
Convert the Rockchip HDMI TX text binding to YAML. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org>
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Laurent Pinchart
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Rockchip DWC HDMI TX Encoder
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============================
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with a companion PHY IP.
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These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
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Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
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following device-specific properties.
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Required properties:
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- compatible: should be one of the following:
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"rockchip,rk3228-dw-hdmi"
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"rockchip,rk3288-dw-hdmi"
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"rockchip,rk3328-dw-hdmi"
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"rockchip,rk3399-dw-hdmi"
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- reg: See dw_hdmi.txt.
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- reg-io-width: See dw_hdmi.txt. Shall be 4.
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- interrupts: HDMI interrupt number
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- clocks: See dw_hdmi.txt.
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- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
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- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
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corresponding to the video input of the controller. The port shall have two
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endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
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- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
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Optional properties
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- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
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or the functionally-reduced I2C master contained in the DWC HDMI. When
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connected to a system I2C master this property contains a phandle to that
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I2C master controller.
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- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
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- clock-names: May contain "cec" as defined in dw_hdmi.txt.
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- clock-names: May contain "grf", power for grf io.
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- clock-names: May contain "vpll", external clock for some hdmi phy.
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- phys: from general PHY binding: the phandle for the PHY device.
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- phy-names: Should be "hdmi" if phys references an external phy.
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Optional pinctrl entry:
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- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
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will switch to the unwedge pinctrl state for 10ms if it ever gets an
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i2c timeout. It's intended that this unwedge pinctrl entry will
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cause the SDA line to be driven low to work around a hardware
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errata.
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Example:
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hdmi: hdmi@ff980000 {
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compatible = "rockchip,rk3288-dw-hdmi";
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reg = <0xff980000 0x20000>;
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reg-io-width = <4>;
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ddc-i2c-bus = <&i2c5>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
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clock-names = "iahb", "isfr";
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ports {
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hdmi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_hdmi>;
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};
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hdmi_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_hdmi>;
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};
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};
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};
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};
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@ -0,0 +1,156 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip DWC HDMI TX Encoder
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maintainers:
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- Mark Yao <markyao0591@gmail.com>
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description: |
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with a companion PHY IP.
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allOf:
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- $ref: ../bridge/synopsys,dw-hdmi.yaml#
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properties:
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compatible:
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enum:
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- rockchip,rk3228-dw-hdmi
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- rockchip,rk3288-dw-hdmi
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- rockchip,rk3328-dw-hdmi
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- rockchip,rk3399-dw-hdmi
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reg-io-width:
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const: 4
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clocks:
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minItems: 2
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maxItems: 5
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items:
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- {}
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- {}
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# The next three clocks are all optional, but shall be specified in this
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# order when present.
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- description: The HDMI CEC controller main clock
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- description: Power for GRF IO
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- description: External clock for some HDMI PHY
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clock-names:
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minItems: 2
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maxItems: 5
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items:
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- {}
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- {}
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- enum:
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- cec
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- grf
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- vpll
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- enum:
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- grf
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- vpll
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- const: vpll
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ddc-i2c-bus:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The HDMI DDC bus can be connected to either a system I2C master or the
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functionally-reduced I2C master contained in the DWC HDMI. When connected
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to a system I2C master this property contains a phandle to that I2C
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master controller.
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phys:
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maxItems: 1
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description: The HDMI PHY
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phy-names:
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const: hdmi
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pinctrl-names:
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description:
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The unwedge pinctrl entry shall drive the DDC SDA line low. This is
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intended to work around a hardware errata that can cause the DDC I2C
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bus to be wedged.
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items:
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- const: default
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- const: unwedge
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: Input of the DWC HDMI TX
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properties:
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endpoint@0:
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$ref: /schemas/graph.yaml#/properties/endpoint
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description: Connection to the VOPB
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endpoint@1:
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$ref: /schemas/graph.yaml#/properties/endpoint
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description: Connection to the VOPL
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required:
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- endpoint@0
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- endpoint@1
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required:
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- port
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to the GRF to mux vopl/vopb.
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required:
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- compatible
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- reg
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- reg-io-width
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- clocks
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- clock-names
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- interrupts
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- ports
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- rockchip,grf
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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hdmi: hdmi@ff980000 {
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compatible = "rockchip,rk3288-dw-hdmi";
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reg = <0xff980000 0x20000>;
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reg-io-width = <4>;
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ddc-i2c-bus = <&i2c5>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
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clock-names = "iahb", "isfr";
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ports {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_hdmi>;
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};
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hdmi_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_hdmi>;
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};
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};
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};
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};
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...
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