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drm/amd/display: Get dprefclk ss percentage from vbios

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Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hersen Wu
2017-04-28 16:21:38 -04:00
committed by Alex Deucher
parent 9c3b2b50b3
commit 7d091f7a44
3 changed files with 51 additions and 48 deletions
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40
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@@ -1070,7 +1070,6 @@ static enum bp_result get_ss_info_v4_1(
{ {
enum bp_result result = BP_RESULT_OK; enum bp_result result = BP_RESULT_OK;
struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
struct atom_smu_info_v3_1 *smu_tbl = NULL;
if (!ss_info) if (!ss_info)
return BP_RESULT_BADINPUT; return BP_RESULT_BADINPUT;
@@ -1078,19 +1077,11 @@ static enum bp_result get_ss_info_v4_1(
if (!DATA_TABLES(dce_info)) if (!DATA_TABLES(dce_info))
return BP_RESULT_BADBIOSTABLE; return BP_RESULT_BADBIOSTABLE;
if (!DATA_TABLES(smu_info))
return BP_RESULT_BADBIOSTABLE;
disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
DATA_TABLES(dce_info)); DATA_TABLES(dce_info));
if (!disp_cntl_tbl) if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE; return BP_RESULT_BADBIOSTABLE;
smu_tbl = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
if (!smu_tbl)
return BP_RESULT_BADBIOSTABLE;
ss_info->type.STEP_AND_DELAY_INFO = false; ss_info->type.STEP_AND_DELAY_INFO = false;
ss_info->spread_percentage_divider = 1000; ss_info->spread_percentage_divider = 1000;
/* BIOS no longer uses target clock. Always enable for now */ /* BIOS no longer uses target clock. Always enable for now */
@@ -1123,12 +1114,11 @@ static enum bp_result get_ss_info_v4_1(
ss_info->type.CENTER_MODE = true; ss_info->type.CENTER_MODE = true;
break; break;
case AS_SIGNAL_TYPE_GPU_PLL: case AS_SIGNAL_TYPE_GPU_PLL:
ss_info->spread_spectrum_percentage = /* atom_firmware: DAL only get data from dce_info table.
smu_tbl->gpuclk_ss_percentage; * if data within smu_info is needed for DAL, VBIOS should
ss_info->spread_spectrum_range = * copy it into dce_info
smu_tbl->gpuclk_ss_rate_10hz * 10; */
if (smu_tbl->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) result = BP_RESULT_UNSUPPORTED;
ss_info->type.CENTER_MODE = true;
break; break;
default: default:
result = BP_RESULT_UNSUPPORTED; result = BP_RESULT_UNSUPPORTED;
@@ -1145,7 +1135,6 @@ static enum bp_result get_ss_info_v4_2(
{ {
enum bp_result result = BP_RESULT_OK; enum bp_result result = BP_RESULT_OK;
struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
struct atom_smu_info_v3_1 *smu_tbl = NULL;
if (!ss_info) if (!ss_info)
return BP_RESULT_BADINPUT; return BP_RESULT_BADINPUT;
@@ -1153,19 +1142,11 @@ static enum bp_result get_ss_info_v4_2(
if (!DATA_TABLES(dce_info)) if (!DATA_TABLES(dce_info))
return BP_RESULT_BADBIOSTABLE; return BP_RESULT_BADBIOSTABLE;
if (!DATA_TABLES(smu_info))
return BP_RESULT_BADBIOSTABLE;
disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
DATA_TABLES(dce_info)); DATA_TABLES(dce_info));
if (!disp_cntl_tbl) if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE; return BP_RESULT_BADBIOSTABLE;
smu_tbl = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
if (!smu_tbl)
return BP_RESULT_BADBIOSTABLE;
ss_info->type.STEP_AND_DELAY_INFO = false; ss_info->type.STEP_AND_DELAY_INFO = false;
ss_info->spread_percentage_divider = 1000; ss_info->spread_percentage_divider = 1000;
/* BIOS no longer uses target clock. Always enable for now */ /* BIOS no longer uses target clock. Always enable for now */
@@ -1198,12 +1179,11 @@ static enum bp_result get_ss_info_v4_2(
ss_info->type.CENTER_MODE = true; ss_info->type.CENTER_MODE = true;
break; break;
case AS_SIGNAL_TYPE_GPU_PLL: case AS_SIGNAL_TYPE_GPU_PLL:
ss_info->spread_spectrum_percentage = /* atom_firmware: DAL only get data from dce_info table.
smu_tbl->gpuclk_ss_percentage; * if data within smu_info is needed for DAL, VBIOS should
ss_info->spread_spectrum_range = * copy it into dce_info
smu_tbl->gpuclk_ss_rate_10hz * 10; */
if (smu_tbl->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) result = BP_RESULT_UNSUPPORTED;
ss_info->type.CENTER_MODE = true;
break; break;
default: default:
result = BP_RESULT_UNSUPPORTED; result = BP_RESULT_UNSUPPORTED;

46
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
View File

@@ -218,11 +218,11 @@ static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
(should not be case with CIK) then SW should program all rates (should not be case with CIK) then SW should program all rates
generated according to average value (case as with previous ASICs) generated according to average value (case as with previous ASICs)
*/ */
if (clk_dce->ss_on_gpu_pll && clk_dce->gpu_pll_ss_divider != 0) { if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
struct fixed32_32 ss_percentage = dal_fixed32_32_div_int( struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
dal_fixed32_32_from_fraction( dal_fixed32_32_from_fraction(
clk_dce->gpu_pll_ss_percentage, clk_dce->dprefclk_ss_percentage,
clk_dce->gpu_pll_ss_divider), 200); clk_dce->dprefclk_ss_divider), 200);
struct fixed32_32 adj_dp_ref_clk_khz; struct fixed32_32 adj_dp_ref_clk_khz;
ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one, ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
@@ -480,22 +480,44 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
*/ */
if (result == BP_RESULT_OK && if (result == BP_RESULT_OK &&
info.spread_spectrum_percentage != 0) { info.spread_spectrum_percentage != 0) {
clk_dce->ss_on_gpu_pll = true; clk_dce->ss_on_dprefclk = true;
clk_dce->gpu_pll_ss_divider = info.spread_percentage_divider; clk_dce->dprefclk_ss_divider = info.spread_percentage_divider;
if (info.type.CENTER_MODE == 0) {
/* TODO: Currently for DP Reference clock we
* need only SS percentage for
* downspread */
clk_dce->dprefclk_ss_percentage =
info.spread_spectrum_percentage;
}
return;
}
result = bp->funcs->get_spread_spectrum_info(
bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
/* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
* even if SS not enabled and in that case
* SSInfo.spreadSpectrumPercentage !=0 would be sign
* that SS is enabled
*/
if (result == BP_RESULT_OK &&
info.spread_spectrum_percentage != 0) {
clk_dce->ss_on_dprefclk = true;
clk_dce->dprefclk_ss_divider = info.spread_percentage_divider;
if (info.type.CENTER_MODE == 0) { if (info.type.CENTER_MODE == 0) {
/* Currently for DP Reference clock we /* Currently for DP Reference clock we
* need only SS percentage for * need only SS percentage for
* downspread */ * downspread */
clk_dce->gpu_pll_ss_percentage = clk_dce->dprefclk_ss_percentage =
info.spread_spectrum_percentage; info.spread_spectrum_percentage;
} }
} }
} }
} }
static bool dce_apply_clock_voltage_request( static bool dce_apply_clock_voltage_request(
struct display_clock *clk, struct display_clock *clk,
enum dm_pp_clock_type clocks_type, enum dm_pp_clock_type clocks_type,
@@ -629,9 +651,11 @@ static void dce_disp_clk_construct(
clk_dce->clk_mask = clk_mask; clk_dce->clk_mask = clk_mask;
clk_dce->dfs_bypass_disp_clk = 0; clk_dce->dfs_bypass_disp_clk = 0;
clk_dce->gpu_pll_ss_percentage = 0;
clk_dce->gpu_pll_ss_divider = 1000; clk_dce->dprefclk_ss_percentage = 0;
clk_dce->ss_on_gpu_pll = false; clk_dce->dprefclk_ss_divider = 1000;
clk_dce->ss_on_dprefclk = false;
base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;

13
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
View File

@@ -116,13 +116,12 @@ struct dce_disp_clk {
* This is basically "Crystal Frequency In KHz" (XTALIN) frequency */ * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
int dfs_bypass_disp_clk; int dfs_bypass_disp_clk;
/* Flag for Enabled SS on GPU PLL */ /* Flag for Enabled SS on DPREFCLK */
bool ss_on_gpu_pll; bool ss_on_dprefclk;
/* GPU PLL SS percentage (if down-spread enabled) */ /* DPREFCLK SS percentage (if down-spread enabled) */
int gpu_pll_ss_percentage; int dprefclk_ss_percentage;
/* GPU PLL SS percentage Divider (100 or 1000) */ /* DPREFCLK SS percentage Divider (100 or 1000) */
int gpu_pll_ss_divider; int dprefclk_ss_divider;
/* max disp_clk from PPLIB for max validation display clock*/ /* max disp_clk from PPLIB for max validation display clock*/
int max_displ_clk_in_khz; int max_displ_clk_in_khz;