Texas Instruments K3 SoC family changes for 5.5
- Add USB support for J721E - Add mailbox support for AM65x and J721E - Add MMC/SD support for J721E - Disable WP for AM654 MMC0 -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEtQ6szHmfiBT7fujkyvq9MXlQGhEFAl3FZUUQHHQta3Jpc3Rv QHRpLmNvbQAKCRDK+r0xeVAaEbIrD/9hGvECYGK081frg4cV50LEWZhdaTkxWeWu UZEfCixUlKMXmkWL0ktY+dny1ZEXQVExkDFDtjGl7lh9FaMo9SDklaLcX2YHfAHn reaT5pndxdrcn83CEHgQSaVx714dS56+g6Gh/RBaUQAKjKeNuKd7INx8zHZ7SMz+ 912S9LDkCZBlgjyNeBQD1wVHyJ+2zsX3ICqQjVB/gD8PZqCq4V1woAPjUQnvQ8di wjWFCZx4sQyY8AbUfOHDPkskl11r7ypCd37M6Ko9SnepDf8FSAjiPIrbyoD3LCHP kdA+kOhqx91mp3AC4HQmQrJeANk51FjxNT1zp6hnI8Ng4vIvnav5vMhx8DE8Go/m sYocnrWJGtL0yLSTrBKDblBccUTNzje2uhANGYbAjsU47lFld6YkMO2Uo9qw8tq2 HdhyW1OE2h6gNnV2gNWKBKboz96RKASY/JUj+YcH66paum841uuP03LI6U/i2TLA QJkw+NolNC/huNOq7+kwW/ip7UrGTwEHJ120Z7IZDksYg9IySc1uXgBQCxe4XaOr Hgtt914T89KLF20mkzMXm7lN/pm4n5YSviAg1Q6R0bfwcphSmbGvsc2vBG0mNpEw GxB0UA92svD+KRUbqXDZ9ec5ir/wI8U855RnNw39q1+vJU56FOVYC65TISyFpjyY 9gUh7L9Ymg== =94Ds -----END PGP SIGNATURE----- Merge tag 'ti-k3-soc-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt Texas Instruments K3 SoC family changes for 5.5 - Add USB support for J721E - Add mailbox support for AM65x and J721E - Add MMC/SD support for J721E - Disable WP for AM654 MMC0 * tag 'ti-k3-soc-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes arm64: dts: ti: k3-am654-base-board: Add disable-wp for mmc0 arm64: dts: ti: j721e-common-proc-board: Add Support for eMMC and SD card arm64: dts: ti: j721e-main: Add SDHCI nodes arm64: dts: ti: k3-j721e-common-proc-board: Add IPC sub-mailbox nodes arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes arm64: dts: ti: k3-am65-base-board: Add IPC sub-mailbox nodes for R5Fs arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes Link: https://lore.kernel.org/r/681f1bb5-d28c-a302-690a-82f0be4a7f34@ti.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
7c3ddc6b03
@ -419,6 +419,114 @@
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reg = <0x00 0x30e00000 0x00 0x1000>;
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#hwlock-cells = <1>;
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};
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mailbox0_cluster0: mailbox@31f80000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f80000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster1: mailbox@31f81000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f81000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster2: mailbox@31f82000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f82000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster3: mailbox@31f83000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f83000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster4: mailbox@31f84000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f84000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster5: mailbox@31f85000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f85000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster6: mailbox@31f86000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f86000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster7: mailbox@31f87000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f87000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster8: mailbox@31f88000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f88000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster9: mailbox@31f89000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f89000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster10: mailbox@31f8a000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f8a000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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mailbox0_cluster11: mailbox@31f8b000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f8b000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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};
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main_gpio0: main_gpio0@600000 {
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@ -221,6 +221,7 @@
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bus-width = <8>;
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non-removable;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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&dwc3_1 {
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@ -280,3 +281,61 @@
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&pcie1_ep {
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status = "disabled";
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};
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&mailbox0_cluster0 {
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interrupts = <164 0>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster1 {
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interrupts = <165 0>;
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster2 {
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status = "disabled";
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};
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&mailbox0_cluster3 {
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status = "disabled";
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};
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&mailbox0_cluster4 {
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status = "disabled";
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};
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&mailbox0_cluster5 {
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status = "disabled";
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};
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&mailbox0_cluster6 {
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status = "disabled";
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};
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&mailbox0_cluster7 {
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status = "disabled";
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};
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&mailbox0_cluster8 {
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status = "disabled";
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};
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&mailbox0_cluster9 {
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status = "disabled";
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};
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&mailbox0_cluster10 {
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status = "disabled";
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};
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&mailbox0_cluster11 {
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status = "disabled";
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};
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@ -41,6 +41,32 @@
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J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
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>;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
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J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
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J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
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J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
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J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
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J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
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J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
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J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
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J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
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>;
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};
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main_usbss0_pins_default: main_usbss0_pins_default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
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>;
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};
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main_usbss1_pins_default: main_usbss1_pins_default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
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>;
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};
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};
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&wkup_pmx0 {
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@ -117,3 +143,139 @@
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&wkup_gpio1 {
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status = "disabled";
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};
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&mailbox0_cluster0 {
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interrupts = <214 0>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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interrupts = <215 0>;
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster2 {
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interrupts = <216 0>;
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mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster3 {
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interrupts = <217 0>;
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mbox_c66_0: mbox-c66-0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_c66_1: mbox-c66-1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster4 {
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interrupts = <218 0>;
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mbox_c71_0: mbox-c71-0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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};
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&mailbox0_cluster5 {
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status = "disabled";
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};
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&mailbox0_cluster6 {
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status = "disabled";
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};
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&mailbox0_cluster7 {
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status = "disabled";
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};
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&mailbox0_cluster8 {
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status = "disabled";
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};
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&mailbox0_cluster9 {
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status = "disabled";
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};
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&mailbox0_cluster10 {
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status = "disabled";
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};
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&mailbox0_cluster11 {
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status = "disabled";
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};
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&main_sdhci0 {
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/* eMMC */
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non-removable;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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&main_sdhci1 {
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/* SD/MMC */
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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||||
};
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||||
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&main_sdhci2 {
|
||||
/* Unused */
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status = "disabled";
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||||
};
|
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&usbss0 {
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||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
ti,usb2-only;
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ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss1_pins_default>;
|
||||
ti,usb2-only;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
@ -95,6 +95,114 @@
|
||||
reg = <0x00 0x30e00000 0x00 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
mailbox0_cluster0: mailbox@31f80000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f80000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster1: mailbox@31f81000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f81000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster2: mailbox@31f82000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f82000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster3: mailbox@31f83000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f83000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster4: mailbox@31f84000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f84000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster5: mailbox@31f85000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f85000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster6: mailbox@31f86000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f86000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster7: mailbox@31f87000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f87000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster8: mailbox@31f88000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f88000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster9: mailbox@31f89000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f89000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster10: mailbox@31f8a000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f8a000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster11: mailbox@31f8b000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f8b000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
@ -378,4 +486,114 @@
|
||||
clocks = <&k3_clks 112 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_sdhci0: sdhci@4f80000 {
|
||||
compatible = "ti,j721e-sdhci-8bit";
|
||||
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
|
||||
assigned-clocks = <&k3_clks 91 1>;
|
||||
assigned-clock-parents = <&k3_clks 91 2>;
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
main_sdhci1: sdhci@4fb0000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
|
||||
assigned-clocks = <&k3_clks 92 0>;
|
||||
assigned-clock-parents = <&k3_clks 92 1>;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
dma-coherent;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
main_sdhci2: sdhci@4f98000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
|
||||
assigned-clocks = <&k3_clks 93 0>;
|
||||
assigned-clock-parents = <&k3_clks 93 1>;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
dma-coherent;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
usbss0: cdns_usb@4104000 {
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x4104000 0x00 0x100>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
|
||||
clock-names = "ref", "lpm";
|
||||
assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
|
||||
assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
usb0: usb@6000000 {
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x00 0x6000000 0x00 0x10000>,
|
||||
<0x00 0x6010000 0x00 0x10000>,
|
||||
<0x00 0x6020000 0x00 0x10000>;
|
||||
reg-names = "otg", "xhci", "dev";
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
|
||||
interrupt-names = "host",
|
||||
"peripheral",
|
||||
"otg";
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
|
||||
usbss1: cdns_usb@4114000 {
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x4114000 0x00 0x100>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
|
||||
clock-names = "ref", "lpm";
|
||||
assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
|
||||
assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
usb1: usb@6400000 {
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x00 0x6400000 0x00 0x10000>,
|
||||
<0x00 0x6410000 0x00 0x10000>,
|
||||
<0x00 0x6420000 0x00 0x10000>;
|
||||
reg-names = "otg", "xhci", "dev";
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
|
||||
interrupt-names = "host",
|
||||
"peripheral",
|
||||
"otg";
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -127,6 +127,8 @@
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
||||
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
|
||||
<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
||||
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user