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drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setup

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This is essentially necessary when uvd/vce dpm is not enabled yet.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2018-05-04 15:20:15 +08:00 committed by Alex Deucher
parent 982b903194
commit 7c2912a26d
1 changed files with 18 additions and 0 deletions
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18
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
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@ -932,6 +932,21 @@ static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
return 0; return 0;
} }
static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
{
struct vega20_hwmgr *data =
(struct vega20_hwmgr *)(hwmgr->backend);
data->uvd_power_gated = true;
data->vce_power_gated = true;
if (data->smu_features[GNLD_DPM_UVD].enabled)
data->uvd_power_gated = false;
if (data->smu_features[GNLD_DPM_VCE].enabled)
data->vce_power_gated = false;
}
static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
@ -954,6 +969,9 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
"[EnableDPMTasks] Failed to enable all smu features!", "[EnableDPMTasks] Failed to enable all smu features!",
return result); return result);
/* Initialize UVD/VCE powergating state */
vega20_init_powergate_state(hwmgr);
result = vega20_setup_default_dpm_tables(hwmgr); result = vega20_setup_default_dpm_tables(hwmgr);
PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE(!result,
"[EnableDPMTasks] Failed to setup default DPM tables!", "[EnableDPMTasks] Failed to setup default DPM tables!",