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clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

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Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Peter De Schrijver 2013-04-03 17:40:38 +03:00 committed by Stephen Warren
parent dd93587be8
commit 7ba28813b4
2 changed files with 7 additions and 0 deletions
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5
drivers/clk/tegra/clk-pll.c
View File

@ -108,6 +108,9 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
if (!(pll->flags & TEGRA_PLL_USE_LOCK)) if (!(pll->flags & TEGRA_PLL_USE_LOCK))
return; return;
if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
return;
val = pll_readl_misc(pll); val = pll_readl_misc(pll);
val |= BIT(pll->params->lock_enable_bit_idx); val |= BIT(pll->params->lock_enable_bit_idx);
pll_writel_misc(val, pll); pll_writel_misc(val, pll);
@ -675,6 +678,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
struct clk *clk; struct clk *clk;
pll_flags |= TEGRA_PLL_BYPASS; pll_flags |= TEGRA_PLL_BYPASS;
pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock); freq_table, lock);
if (IS_ERR(pll)) if (IS_ERR(pll))
@ -698,6 +702,7 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
struct clk *clk; struct clk *clk;
pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock); freq_table, lock);
if (IS_ERR(pll)) if (IS_ERR(pll))

2
drivers/clk/tegra/clk.h
View File

@ -185,6 +185,7 @@ struct tegra_clk_pll_params {
* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
* base register. * base register.
* TEGRA_PLL_BYPASS - PLL has bypass bit * TEGRA_PLL_BYPASS - PLL has bypass bit
* TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
*/ */
struct tegra_clk_pll { struct tegra_clk_pll {
struct clk_hw hw; struct clk_hw hw;
@ -215,6 +216,7 @@ struct tegra_clk_pll {
#define TEGRA_PLLE_CONFIGURE BIT(7) #define TEGRA_PLLE_CONFIGURE BIT(7)
#define TEGRA_PLL_LOCK_MISC BIT(8) #define TEGRA_PLL_LOCK_MISC BIT(8)
#define TEGRA_PLL_BYPASS BIT(9) #define TEGRA_PLL_BYPASS BIT(9)
#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
extern const struct clk_ops tegra_clk_pll_ops; extern const struct clk_ops tegra_clk_pll_ops;
extern const struct clk_ops tegra_clk_plle_ops; extern const struct clk_ops tegra_clk_plle_ops;