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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Ensure that ST0_FR is never set on a 32 bit kernel
  [MIPS] time: Delete weak definition of plat_time_init() due to gcc bug.
  [MIPS] PCI: Make pcibios_fixup_device_resources ignore legacy resources.
  [MIPS] Atlas, Malta: Don't free firmware memory on free_initmem.
  [MIPS] Alchemy: fix off by two error in __fixup_bigphys_addr()
  [MIPS] Alchemy: fix PCI resource conflict
  [MIPS] time: Set up Cobalt's mips_hpt_frequency
This commit is contained in:
Linus Torvalds 2007-12-17 08:41:25 -08:00
commit 7b286af392
10 changed files with 41 additions and 32 deletions
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9
arch/mips/au1000/Kconfig
View File

@ -7,7 +7,6 @@ config MIPS_MTX1
bool "4G Systems MTX-1 board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select RESOURCES_64BIT if PCI
select SOC_AU1500
select SYS_SUPPORTS_LITTLE_ENDIAN
@ -22,7 +21,6 @@ config MIPS_DB1000
select SOC_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select RESOURCES_64BIT if PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_DB1100
@ -44,7 +42,6 @@ config MIPS_DB1500
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
select RESOURCES_64BIT if PCI
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
@ -54,7 +51,6 @@ config MIPS_DB1550
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select RESOURCES_64BIT if PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_MIRAGE
@ -68,7 +64,6 @@ config MIPS_PB1000
select SOC_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select RESOURCES_64BIT if PCI
select SWAP_IO_SPACE
select SYS_SUPPORTS_LITTLE_ENDIAN
@ -77,7 +72,6 @@ config MIPS_PB1100
select SOC_AU1100
select DMA_NONCOHERENT
select HW_HAS_PCI
select RESOURCES_64BIT if PCI
select SWAP_IO_SPACE
select SYS_SUPPORTS_LITTLE_ENDIAN
@ -86,7 +80,6 @@ config MIPS_PB1200
select SOC_AU1200
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select RESOURCES_64BIT if PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_PB1500
@ -94,7 +87,6 @@ config MIPS_PB1500
select SOC_AU1500
select DMA_NONCOHERENT
select HW_HAS_PCI
select RESOURCES_64BIT if PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_PB1550
@ -103,7 +95,6 @@ config MIPS_PB1550
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
select RESOURCES_64BIT if PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_XXS1500

8
arch/mips/au1000/common/pci.c
View File

@ -39,15 +39,15 @@
/* TBD */
static struct resource pci_io_resource = {
.start = (resource_size_t)PCI_IO_START,
.end = (resource_size_t)PCI_IO_END,
.start = PCI_IO_START,
.end = PCI_IO_END,
.name = "PCI IO space",
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.start = (resource_size_t)PCI_MEM_START,
.end = (resource_size_t)PCI_MEM_END,
.start = PCI_MEM_START,
.end = PCI_MEM_END,
.name = "PCI memory space",
.flags = IORESOURCE_MEM
};

9
arch/mips/au1000/common/setup.c
View File

@ -137,12 +137,11 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
#ifdef CONFIG_PCI
{
u32 start, end;
u32 start = (u32)Au1500_PCI_MEM_START;
u32 end = (u32)Au1500_PCI_MEM_END;
start = (u32)Au1500_PCI_MEM_START;
end = (u32)Au1500_PCI_MEM_END;
/* check for pci memory window */
if ((phys_addr >= start) && ((phys_addr + size) < end))
/* Check for PCI memory window */
if (phys_addr >= start && (phys_addr + size - 1) <= end)
return (phys_t)
((phys_addr - start) + Au1500_PCI_MEM_START);
}

21
arch/mips/cobalt/time.c
View File

@ -27,9 +27,28 @@
void __init plat_time_init(void)
{
u32 start, end;
int i = HZ / 10;
setup_pit_timer();
gt641xx_set_base_clock(GT641XX_BASE_CLOCK);
mips_timer_state = gt641xx_timer0_state;
/*
* MIPS counter frequency is measured during a 100msec interval
* using GT64111 timer0.
*/
while (!gt641xx_timer0_state())
;
start = read_c0_count();
while (i--)
while (!gt641xx_timer0_state())
;
end = read_c0_count();
mips_hpt_frequency = (end - start) * 10;
printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency);
}

3
arch/mips/kernel/process.c
View File

@ -77,9 +77,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
unsigned long status;
/* New thread loses kernel privileges. */
status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK);
status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
#ifdef CONFIG_64BIT
status &= ~ST0_FR;
status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR;
#endif
status |= KU_USER;

4
arch/mips/kernel/time.c
View File

@ -109,10 +109,6 @@ void __cpuinit clockevent_set_clock(struct clock_event_device *cd,
cd->mult = (u32) temp;
}
void __init __weak plat_time_init(void)
{
}
/*
* This function exists in order to cause an error due to a duplicate
* definition if platform code should have its own implementation. The hook

6
arch/mips/kernel/traps.c
View File

@ -1317,12 +1317,12 @@ void __init per_cpu_trap_init(void)
#endif
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
status_set |= ST0_XX;
if (cpu_has_dsp)
status_set |= ST0_MX;
change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
status_set);
if (cpu_has_dsp)
set_c0_status(ST0_MX);
#ifdef CONFIG_CPU_MIPSR2
if (cpu_has_mips_r2) {
unsigned int enable = 0x0000000f;

2
arch/mips/mips-boards/generic/memory.c
View File

@ -169,6 +169,7 @@ void __init prom_meminit(void)
void __init prom_free_prom_memory(void)
{
#if 0 /* for now ... */
unsigned long addr;
int i;
@ -180,4 +181,5 @@ void __init prom_free_prom_memory(void)
free_init_pages("prom memory",
addr, addr + boot_mem_map.map[i].size);
}
#endif
}

2
arch/mips/pci/pci.c
View File

@ -242,6 +242,8 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev,
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
if (!dev->resource[i].start)
continue;
if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
continue;
if (dev->resource[i].flags & IORESOURCE_IO)
offset = hose->io_offset;
else if (dev->resource[i].flags & IORESOURCE_MEM)

9
include/asm-mips/mach-au1x00/au1000.h
View File

@ -1680,10 +1680,11 @@ enum soc_au1200_ints {
#define Au1500_PCI_MEM_START 0x440000000ULL
#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
#define PCI_IO_START (Au1500_PCI_IO_START + 0x1000)
#define PCI_IO_END (Au1500_PCI_IO_END)
#define PCI_MEM_START (Au1500_PCI_MEM_START)
#define PCI_MEM_END (Au1500_PCI_MEM_END)
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x000FFFFF
#define PCI_MEM_START 0x40000000
#define PCI_MEM_END 0x4FFFFFFF
#define PCI_FIRST_DEVFN (0<<3)
#define PCI_LAST_DEVFN (19<<3)