Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
Pull RDMA subsystem updates from Jason Gunthorpe:
"Overall this cycle did not have any major excitement, and did not
require any shared branch with netdev.
Lots of driver updates, particularly of the scale-up and performance
variety. The largest body of core work was Parav's patches fixing and
restructing some of the core code to make way for future RDMA
containerization.
Summary:
- misc small driver fixups to
bnxt_re/hfi1/qib/hns/ocrdma/rdmavt/vmw_pvrdma/nes
- several major feature adds to bnxt_re driver: SRIOV VF RoCE
support, HugePages support, extended hardware stats support, and
SRQ support
- a notable number of fixes to the i40iw driver from debugging scale
up testing
- more work to enable the new hip08 chip in the hns driver
- misc small ULP fixups to srp/srpt//ipoib
- preparation for srp initiator and target to support the RDMA-CM
protocol for connections
- add RDMA-CM support to srp initiator, srp target is still a WIP
- fixes for a couple of places where ipoib could spam the dmesg log
- fix encode/decode of FDR/EDR data rates in the core
- many patches from Parav with ongoing work to clean up
inconsistencies and bugs in RoCE support around the rdma_cm
- mlx5 driver support for the userspace features 'thread domain',
'wallclock timestamps' and 'DV Direct Connected transport'. Support
for the firmware dual port rocee capability
- core support for more than 32 rdma devices in the char dev
allocation
- kernel doc updates from Randy Dunlap
- new netlink uAPI for inspecting RDMA objects similar in spirit to 'ss'
- one minor change to the kobject code acked by Greg KH"
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (259 commits)
RDMA/nldev: Provide detailed QP information
RDMA/nldev: Provide global resource utilization
RDMA/core: Add resource tracking for create and destroy PDs
RDMA/core: Add resource tracking for create and destroy CQs
RDMA/core: Add resource tracking for create and destroy QPs
RDMA/restrack: Add general infrastructure to track RDMA resources
RDMA/core: Save kernel caller name when creating PD and CQ objects
RDMA/core: Use the MODNAME instead of the function name for pd callers
RDMA: Move enum ib_cq_creation_flags to uapi headers
IB/rxe: Change RDMA_RXE kconfig to use select
IB/qib: remove qib_keys.c
IB/mthca: remove mthca_user.h
RDMA/cm: Fix access to uninitialized variable
RDMA/cma: Use existing netif_is_bond_master function
IB/core: Avoid SGID attributes query while converting GID from OPA to IB
RDMA/mlx5: Avoid memory leak in case of XRCD dealloc failure
IB/umad: Fix use of unprotected device pointer
IB/iser: Combine substrings for three messages
IB/iser: Delete an unnecessary variable initialisation in iser_send_data_out()
IB/iser: Delete an error message for a failed memory allocation in iser_send_data_out()
...
This commit is contained in:
@@ -82,6 +82,15 @@ struct bnxt_re_qp_resp {
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__u32 rsvd;
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};
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struct bnxt_re_srq_req {
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__u64 srqva;
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__u64 srq_handle;
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};
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struct bnxt_re_srq_resp {
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__u32 srqid;
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};
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enum bnxt_re_shpg_offt {
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BNXT_RE_BEG_RESV_OFFT = 0x00,
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BNXT_RE_AVID_OFFT = 0x10,
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@@ -402,13 +402,18 @@ struct ib_uverbs_create_cq {
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__u64 driver_data[0];
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};
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enum ib_uverbs_ex_create_cq_flags {
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IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION = 1 << 0,
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IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN = 1 << 1,
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};
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struct ib_uverbs_ex_create_cq {
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__u64 user_handle;
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__u32 cqe;
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__u32 comp_vector;
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__s32 comp_channel;
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__u32 comp_mask;
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__u32 flags;
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__u32 flags; /* bitmask of ib_uverbs_ex_create_cq_flags */
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__u32 reserved;
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};
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@@ -449,7 +454,7 @@ struct ib_uverbs_wc {
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__u32 vendor_err;
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__u32 byte_len;
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union {
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__u32 imm_data;
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__be32 imm_data;
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__u32 invalidate_rkey;
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} ex;
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__u32 qp_num;
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@@ -765,7 +770,7 @@ struct ib_uverbs_send_wr {
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__u32 opcode;
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__u32 send_flags;
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union {
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__u32 imm_data;
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__be32 imm_data;
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__u32 invalidate_rkey;
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} ex;
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union {
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@@ -97,8 +97,8 @@ struct mlx4_ib_create_srq_resp {
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};
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struct mlx4_ib_create_qp_rss {
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__u64 rx_hash_fields_mask;
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__u8 rx_hash_function;
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__u64 rx_hash_fields_mask; /* Use enum mlx4_ib_rx_hash_fields */
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__u8 rx_hash_function; /* Use enum mlx4_ib_rx_hash_function_flags */
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__u8 reserved[7];
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__u8 rx_hash_key[40];
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__u32 comp_mask;
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@@ -152,7 +152,8 @@ enum mlx4_ib_rx_hash_fields {
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MLX4_IB_RX_HASH_SRC_PORT_TCP = 1 << 4,
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MLX4_IB_RX_HASH_DST_PORT_TCP = 1 << 5,
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MLX4_IB_RX_HASH_SRC_PORT_UDP = 1 << 6,
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MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7
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MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7,
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MLX4_IB_RX_HASH_INNER = 1ULL << 31,
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};
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#endif /* MLX4_ABI_USER_H */
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@@ -41,6 +41,9 @@ enum {
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MLX5_QP_FLAG_SIGNATURE = 1 << 0,
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MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
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MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
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MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
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MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
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MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
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};
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enum {
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@@ -121,10 +124,12 @@ struct mlx5_ib_alloc_ucontext_resp {
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__u8 cqe_version;
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__u8 cmds_supp_uhw;
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__u8 eth_min_inline;
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__u8 reserved2;
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__u8 clock_info_versions;
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__u64 hca_core_clock_offset;
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__u32 log_uar_size;
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__u32 num_uars_per_page;
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__u32 num_dyn_bfregs;
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__u32 reserved3;
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};
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struct mlx5_ib_alloc_pd_resp {
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@@ -280,8 +285,11 @@ struct mlx5_ib_create_qp {
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__u32 rq_wqe_shift;
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__u32 flags;
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__u32 uidx;
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__u32 reserved0;
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__u64 sq_buf_addr;
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__u32 bfreg_index;
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union {
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__u64 sq_buf_addr;
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__u64 access_key;
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};
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};
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/* RX Hash function flags */
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@@ -307,7 +315,7 @@ enum mlx5_rx_hash_fields {
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MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
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MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
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/* Save bits for future fields */
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MLX5_RX_HASH_INNER = 1 << 31
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MLX5_RX_HASH_INNER = (1UL << 31),
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};
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struct mlx5_ib_create_qp_rss {
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@@ -354,6 +362,11 @@ struct mlx5_ib_create_ah_resp {
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__u8 reserved[6];
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};
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struct mlx5_ib_modify_qp_resp {
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__u32 response_length;
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__u32 dctn;
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};
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struct mlx5_ib_create_wq_resp {
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__u32 response_length;
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__u32 reserved;
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@@ -368,4 +381,36 @@ struct mlx5_ib_modify_wq {
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__u32 comp_mask;
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__u32 reserved;
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};
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struct mlx5_ib_clock_info {
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__u32 sign;
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__u32 resv;
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__u64 nsec;
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__u64 cycles;
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__u64 frac;
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__u32 mult;
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__u32 shift;
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__u64 mask;
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__u64 overflow_period;
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};
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enum mlx5_ib_mmap_cmd {
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MLX5_IB_MMAP_REGULAR_PAGE = 0,
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MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
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MLX5_IB_MMAP_WC_PAGE = 2,
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MLX5_IB_MMAP_NC_PAGE = 3,
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/* 5 is chosen in order to be compatible with old versions of libmlx5 */
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MLX5_IB_MMAP_CORE_CLOCK = 5,
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MLX5_IB_MMAP_ALLOC_WC = 6,
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MLX5_IB_MMAP_CLOCK_INFO = 7,
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};
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enum {
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MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
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};
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/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
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enum {
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MLX5_IB_CLOCK_INFO_V1 = 0,
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};
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#endif /* MLX5_ABI_USER_H */
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@@ -236,6 +236,10 @@ enum rdma_nldev_command {
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RDMA_NLDEV_CMD_PORT_NEW,
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RDMA_NLDEV_CMD_PORT_DEL,
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RDMA_NLDEV_CMD_RES_GET, /* can dump */
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RDMA_NLDEV_CMD_RES_QP_GET, /* can dump */
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RDMA_NLDEV_NUM_OPS
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};
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@@ -303,6 +307,51 @@ enum rdma_nldev_attr {
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RDMA_NLDEV_ATTR_DEV_NODE_TYPE, /* u8 */
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RDMA_NLDEV_ATTR_RES_SUMMARY, /* nested table */
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RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY, /* nested table */
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RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_NAME, /* string */
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RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_CURR, /* u64 */
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RDMA_NLDEV_ATTR_RES_QP, /* nested table */
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RDMA_NLDEV_ATTR_RES_QP_ENTRY, /* nested table */
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/*
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* Local QPN
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*/
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RDMA_NLDEV_ATTR_RES_LQPN, /* u32 */
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/*
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* Remote QPN,
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* Applicable for RC and UC only IBTA 11.2.5.3 QUERY QUEUE PAIR
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*/
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RDMA_NLDEV_ATTR_RES_RQPN, /* u32 */
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/*
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* Receive Queue PSN,
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* Applicable for RC and UC only 11.2.5.3 QUERY QUEUE PAIR
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*/
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RDMA_NLDEV_ATTR_RES_RQ_PSN, /* u32 */
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/*
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* Send Queue PSN
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*/
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RDMA_NLDEV_ATTR_RES_SQ_PSN, /* u32 */
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RDMA_NLDEV_ATTR_RES_PATH_MIG_STATE, /* u8 */
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/*
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* QP types as visible to RDMA/core, the reserved QPT
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* are not exported through this interface.
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*/
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RDMA_NLDEV_ATTR_RES_TYPE, /* u8 */
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RDMA_NLDEV_ATTR_RES_STATE, /* u8 */
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/*
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* Process ID which created object,
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* in case of kernel origin, PID won't exist.
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*/
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RDMA_NLDEV_ATTR_RES_PID, /* u32 */
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/*
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* The name of process created following resource.
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* It will exist only for kernel objects.
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* For user created objects, the user is supposed
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* to read /proc/PID/comm file.
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*/
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RDMA_NLDEV_ATTR_RES_KERN_NAME, /* string */
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RDMA_NLDEV_ATTR_MAX
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};
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#endif /* _UAPI_RDMA_NETLINK_H */
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@@ -52,12 +52,14 @@
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#define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */
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#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */
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#define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */
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#define PVRDMA_UAR_QP_SEND BIT(30) /* Send bit. */
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#define PVRDMA_UAR_QP_RECV BIT(31) /* Recv bit. */
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#define PVRDMA_UAR_QP_SEND (1 << 30) /* Send bit. */
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#define PVRDMA_UAR_QP_RECV (1 << 31) /* Recv bit. */
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#define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */
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#define PVRDMA_UAR_CQ_ARM_SOL BIT(29) /* Arm solicited bit. */
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#define PVRDMA_UAR_CQ_ARM BIT(30) /* Arm bit. */
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#define PVRDMA_UAR_CQ_POLL BIT(31) /* Poll bit. */
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#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) /* Arm solicited bit. */
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#define PVRDMA_UAR_CQ_ARM (1 << 30) /* Arm bit. */
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#define PVRDMA_UAR_CQ_POLL (1 << 31) /* Poll bit. */
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#define PVRDMA_UAR_SRQ_OFFSET 8 /* SRQ doorbell. */
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#define PVRDMA_UAR_SRQ_RECV (1 << 30) /* Recv bit. */
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enum pvrdma_wr_opcode {
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PVRDMA_WR_RDMA_WRITE,
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