amdgpu: Wrap FPU dependent functions in dc20
dc20 containes several FPU-dependent functions without proper FPU kernel mode enable/disable wrappers. Add the required wrappers for both x86 and POWER. This enables Navi DC20 support for POWER systems. v2: fix compilation Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2887,12 +2887,19 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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bool voltage_supported = false;
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bool full_pstate_supported = false;
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bool dummy_pstate_supported = false;
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double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
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context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = dc->debug.disable_dram_clock_change_vactive_support;
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double p_state_latency_us;
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if (fast_validate)
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return dcn20_validate_bandwidth_internal(dc, context, true);
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DC_FP_START();
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p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
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context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
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dc->debug.disable_dram_clock_change_vactive_support;
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if (fast_validate) {
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voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);
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DC_FP_END();
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return voltage_supported;
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}
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// Best case, we support full UCLK switch latency
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voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
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@ -2921,6 +2928,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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restore_dml_state:
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context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
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DC_FP_END();
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return voltage_supported;
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}
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@ -3442,6 +3450,8 @@ static bool dcn20_resource_construct(
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enum dml_project dml_project_version =
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get_dml_project_version(ctx->asic_id.hw_internal_rev);
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DC_FP_START();
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ctx->dc_bios->regs = &bios_regs;
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pool->base.funcs = &dcn20_res_pool_funcs;
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@ -3739,10 +3749,12 @@ static bool dcn20_resource_construct(
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pool->base.oem_device = NULL;
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}
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DC_FP_END();
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return true;
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create_fail:
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DC_FP_END();
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dcn20_resource_destruct(pool);
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return false;
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