From f63834e6c6145fb7667ef0c645cbc52313e71c69 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 18 Oct 2013 20:02:29 -0300 Subject: [PATCH 1/3] ARM: mvebu: Add Core Divider clock device-tree binding The Armada 370/XP SoCs have a Core Divider clock providing several clocks. For now, only the NAND clock is supported. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- .../bindings/clock/mvebu-corediv-clock.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt new file mode 100644 index 000000000000..c62391fc0e39 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt @@ -0,0 +1,19 @@ +* Core Divider Clock bindings for Marvell MVEBU SoCs + +The following is a list of provided IDs and clock names on Armada 370/XP: + 0 = nand (NAND clock) + +Required properties: +- compatible : must be "marvell,armada-370-corediv-clock" +- reg : must be the register address of Core Divider control register +- #clock-cells : from common clock binding; shall be set to 1 +- clocks : must be set to the parent's phandle + +Example: + +corediv_clk: corediv-clocks@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&pll>; +}; From 4675cf577e4bbe179df1cf10a6fab8854333d99d Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 18 Oct 2013 20:02:30 -0300 Subject: [PATCH 2/3] ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed other clocks. This commit adds a DT representation of this clock through a fixed-clock compatible node. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 534e1be80df2..13efe05a8c9f 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -251,4 +251,13 @@ }; }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; }; From f039dfb51b36a2d7e4ac25e65ffbd03e3ac77a0c Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 18 Oct 2013 20:02:31 -0300 Subject: [PATCH 3/3] ARM: mvebu: Add the core-divider clock to Armada 370/XP The Armada 370/XP SoC has a clock provider called "Core Divider", that is derived from a fixed 2 GHz PLL clock. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 13efe05a8c9f..00d6a798c705 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -138,6 +138,14 @@ status = "disabled"; }; + coredivclk: corediv-clock@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>;