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drm/amd/display: fix 64bit division issue on 32bit OS

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Replace "/" with div_u64 for 64bit division on 32bit OS.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lang Yu 2021-01-27 10:32:55 +08:00 committed by Alex Deucher
parent 6fce5bcee5
commit 7a03fdf628
3 changed files with 5 additions and 4 deletions
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4
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -3688,8 +3688,8 @@ uint32_t dc_link_bandwidth_kbps(
* but the difference is minimal and is in a safe direction, * but the difference is minimal and is in a safe direction,
* which all works well around potential ambiguity of DP 1.4a spec. * which all works well around potential ambiguity of DP 1.4a spec.
*/ */
link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, long long fec_link_bw_kbps = link_bw_kbps * 970LL;
link_bw_kbps, 32); link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
} }
return link_bw_kbps; return link_bw_kbps;

2
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View File

@ -240,7 +240,7 @@ static bool calc_fb_divider_checking_tolerance(
pll_settings->calculated_pix_clk_100hz = pll_settings->calculated_pix_clk_100hz =
actual_calculated_clock_100hz; actual_calculated_clock_100hz;
pll_settings->vco_freq = pll_settings->vco_freq =
actual_calculated_clock_100hz * post_divider / 10; div_u64(actual_calculated_clock_100hz * post_divider, 10);
return true; return true;
} }
return false; return false;

3
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -3506,7 +3506,8 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
// FCLK:UCLK ratio is 1.08 // FCLK:UCLK ratio is 1.08
min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1000000);
calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
min_dcfclk : min_fclk_required_by_uclk; min_dcfclk : min_fclk_required_by_uclk;