forked from Minki/linux
Staging: vme: Correct checkpatch errors
Correct numerous checkpatch errors in the vme driver. Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Martyn Welch
Greg Kroah-Hartman
parent
48d9356e77
commit
7946328faf
@ -26,9 +26,9 @@
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <linux/time.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include "../vme.h"
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#include "../vme_bridge.h"
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@ -1684,9 +1684,8 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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dev_info(&pdev->dev, "Slot ID is %d\n",
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ca91cx42_slot_get(ca91cx42_bridge));
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if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) {
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if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
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dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
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}
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/* Need to save ca91cx42_bridge pointer locally in link list for use in
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* ca91cx42_remove()
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@ -26,9 +26,9 @@
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <linux/time.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include "../vme.h"
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#include "../vme_bridge.h"
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@ -40,27 +40,6 @@ static void tsi148_remove(struct pci_dev *);
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static void __exit tsi148_exit(void);
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int tsi148_slave_set(struct vme_slave_resource *, int, unsigned long long,
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unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t);
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int tsi148_slave_get(struct vme_slave_resource *, int *, unsigned long long *,
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unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *);
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int tsi148_master_get(struct vme_master_resource *, int *, unsigned long long *,
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unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *);
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int tsi148_master_set(struct vme_master_resource *, int, unsigned long long,
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unsigned long long, vme_address_t, vme_cycle_t, vme_width_t);
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ssize_t tsi148_master_read(struct vme_master_resource *, void *, size_t,
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loff_t);
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ssize_t tsi148_master_write(struct vme_master_resource *, void *, size_t,
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loff_t);
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unsigned int tsi148_master_rmw(struct vme_master_resource *, unsigned int,
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unsigned int, unsigned int, loff_t);
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int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *,
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struct vme_dma_attr *, size_t);
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int tsi148_dma_list_exec(struct vme_dma_list *);
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int tsi148_dma_list_empty(struct vme_dma_list *);
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int tsi148_generate_irq(int, int);
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/* Module parameter */
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static int err_chk;
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static int geoid;
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@ -122,7 +101,7 @@ static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
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u32 serviced = 0;
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for (i = 0; i < 4; i++) {
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if(stat & TSI148_LCSR_INTS_LMS[i]) {
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if (stat & TSI148_LCSR_INTS_LMS[i]) {
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/* We only enable interrupts if the callback is set */
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bridge->lm_callback[i](i);
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serviced |= TSI148_LCSR_INTC_LMC[i];
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@ -147,7 +126,7 @@ static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
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bridge = tsi148_bridge->driver_priv;
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for (i = 0; i < 4; i++) {
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if(stat & TSI148_LCSR_INTS_MBS[i]) {
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if (stat & TSI148_LCSR_INTS_MBS[i]) {
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val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
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dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
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": 0x%x\n", i, val);
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@ -203,13 +182,12 @@ static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
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reg_join(error_addr_high, error_addr_low, &error_addr);
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/* Check for exception register overflow (we have lost error data) */
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if(error_attrib & TSI148_LCSR_VEAT_VEOF) {
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if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
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dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
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"Occurred\n");
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}
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error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error),
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GFP_ATOMIC);
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error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
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if (error) {
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error->address = error_addr;
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error->attributes = error_attrib;
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@ -251,10 +229,9 @@ static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
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for (i = 7; i > 0; i--) {
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if (stat & (1 << i)) {
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/*
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* Note: Even though the registers are defined
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* as 32-bits in the spec, we only want to issue
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* 8-bit IACK cycles on the bus, read from offset
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* 3.
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* Note: Even though the registers are defined as
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* 32-bits in the spec, we only want to issue 8-bit
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* IACK cycles on the bus, read from offset 3.
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*/
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vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
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@ -288,9 +265,8 @@ static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
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/* Only look at unmasked interrupts */
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stat &= enable;
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if (unlikely(!stat)) {
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if (unlikely(!stat))
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return IRQ_NONE;
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}
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/* Call subhandlers as appropriate */
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/* DMA irqs */
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@ -522,7 +498,9 @@ static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
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/* Iterate through errors */
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list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
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vme_err = list_entry(err_pos, struct vme_bus_error, list);
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if((vme_err->address >= address) && (vme_err->address < bound)){
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if ((vme_err->address >= address) &&
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(vme_err->address < bound)) {
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valid = vme_err;
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break;
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}
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@ -555,7 +533,9 @@ static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
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list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
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vme_err = list_entry(err_pos, struct vme_bus_error, list);
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if((vme_err->address >= address) && (vme_err->address < bound)){
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if ((vme_err->address >= address) &&
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(vme_err->address < bound)) {
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list_del(err_pos);
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kfree(vme_err);
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}
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@ -844,9 +824,8 @@ static int tsi148_alloc_resource(struct vme_master_resource *image,
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}
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/* Exit here if size is zero */
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if (size == 0) {
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if (size == 0)
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return 0;
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}
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if (image->bus_resource.name == NULL) {
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image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
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@ -912,7 +891,7 @@ static void tsi148_free_resource(struct vme_master_resource *image)
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/*
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* Set the attributes of an outbound window.
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*/
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int tsi148_master_set( struct vme_master_resource *image, int enabled,
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int tsi148_master_set(struct vme_master_resource *image, int enabled,
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unsigned long long vme_base, unsigned long long size,
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vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
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{
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@ -1148,7 +1127,7 @@ err_window:
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*
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* XXX Not parsing prefetch information.
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*/
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int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
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int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
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unsigned long long *vme_base, unsigned long long *size,
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vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
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{
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@ -1225,17 +1204,17 @@ int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
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*cycle |= VME_2eSST320;
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/* Setup cycle types */
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if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_SCT)
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if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
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*cycle |= VME_SCT;
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if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_BLT)
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if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
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*cycle |= VME_BLT;
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if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_MBLT)
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if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
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*cycle |= VME_MBLT;
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if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eVME)
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if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
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*cycle |= VME_2eVME;
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if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSST)
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if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
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*cycle |= VME_2eSST;
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if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSSTB)
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if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
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*cycle |= VME_2eSSTB;
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if (ctl & TSI148_LCSR_OTAT_SUP)
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@ -1258,7 +1237,7 @@ int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
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}
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int tsi148_master_get( struct vme_master_resource *image, int *enabled,
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int tsi148_master_get(struct vme_master_resource *image, int *enabled,
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unsigned long long *vme_base, unsigned long long *size,
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vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
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{
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@ -1300,7 +1279,7 @@ ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
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vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
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count);
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if(vme_err != NULL) {
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if (vme_err != NULL) {
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dev_err(image->parent->parent, "First VME read error detected "
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"an at address 0x%llx\n", vme_err->address);
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retval = vme_err->address - (vme_base + offset);
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@ -1363,7 +1342,7 @@ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
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vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
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count);
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if(vme_err != NULL) {
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if (vme_err != NULL) {
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dev_warn(tsi148_bridge->parent, "First VME write error detected"
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" an at address 0x%llx\n", vme_err->address);
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retval = vme_err->address - (vme_base + offset);
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@ -1456,21 +1435,21 @@ static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr,
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}
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/* Setup cycle types */
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if (cycle & VME_SCT) {
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if (cycle & VME_SCT)
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*attr |= TSI148_LCSR_DSAT_TM_SCT;
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}
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if (cycle & VME_BLT) {
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if (cycle & VME_BLT)
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*attr |= TSI148_LCSR_DSAT_TM_BLT;
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}
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if (cycle & VME_MBLT) {
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if (cycle & VME_MBLT)
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*attr |= TSI148_LCSR_DSAT_TM_MBLT;
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}
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if (cycle & VME_2eVME) {
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if (cycle & VME_2eVME)
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*attr |= TSI148_LCSR_DSAT_TM_2eVME;
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}
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if (cycle & VME_2eSST) {
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if (cycle & VME_2eSST)
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*attr |= TSI148_LCSR_DSAT_TM_2eSST;
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}
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if (cycle & VME_2eSSTB) {
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dev_err(dev, "Currently not setting Broadcast Select "
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"Registers\n");
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@ -1550,21 +1529,21 @@ static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr,
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}
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/* Setup cycle types */
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if (cycle & VME_SCT) {
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if (cycle & VME_SCT)
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*attr |= TSI148_LCSR_DDAT_TM_SCT;
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}
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if (cycle & VME_BLT) {
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if (cycle & VME_BLT)
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*attr |= TSI148_LCSR_DDAT_TM_BLT;
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}
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if (cycle & VME_MBLT) {
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if (cycle & VME_MBLT)
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*attr |= TSI148_LCSR_DDAT_TM_MBLT;
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}
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if (cycle & VME_2eVME) {
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if (cycle & VME_2eVME)
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*attr |= TSI148_LCSR_DDAT_TM_2eVME;
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}
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if (cycle & VME_2eSST) {
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if (cycle & VME_2eSST)
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*attr |= TSI148_LCSR_DDAT_TM_2eSST;
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}
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if (cycle & VME_2eSSTB) {
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dev_err(dev, "Currently not setting Broadcast Select "
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"Registers\n");
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@ -1630,7 +1609,7 @@ static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr,
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/*
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* Add a link list descriptor to the list
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*/
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int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
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int tsi148_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
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struct vme_dma_attr *dest, size_t count)
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{
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struct tsi148_dma_entry *entry, *prev;
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@ -1645,8 +1624,7 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
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tsi148_bridge = list->parent->parent;
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/* Descriptor must be aligned on 64-bit boundaries */
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entry = (struct tsi148_dma_entry *)kmalloc(
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sizeof(struct tsi148_dma_entry), GFP_KERNEL);
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entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
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if (entry == NULL) {
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dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
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"dma resource structure\n");
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@ -1676,13 +1654,13 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
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entry->descriptor.dsal = pattern_attr->pattern;
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entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
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/* Default behaviour is 32 bit pattern */
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if (pattern_attr->type & VME_DMA_PATTERN_BYTE) {
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if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
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entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
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}
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/* It seems that the default behaviour is to increment */
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if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) {
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if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
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entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
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}
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break;
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case VME_DMA_PCI:
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pci_attr = (struct vme_dma_pci *)src->private;
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@ -1705,7 +1683,7 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
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retval = tsi148_dma_set_vme_src_attributes(
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tsi148_bridge->parent, &(entry->descriptor.dsat),
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vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
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if(retval < 0 )
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if (retval < 0)
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goto err_source;
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break;
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default:
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@ -1743,7 +1721,7 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
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retval = tsi148_dma_set_vme_dest_attributes(
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tsi148_bridge->parent, &(entry->descriptor.ddat),
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vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
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if(retval < 0 )
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if (retval < 0)
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goto err_dest;
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break;
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default:
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@ -1760,7 +1738,7 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
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list_add_tail(&(entry->list), &(list->entries));
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/* Fill out previous descriptors "Next Address" */
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if(entry->list.prev != &(list->entries)){
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if (entry->list.prev != &(list->entries)) {
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prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
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list);
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/* We need the bus address for the pointer */
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@ -1825,7 +1803,7 @@ int tsi148_dma_list_exec(struct vme_dma_list *list)
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channel = ctrlr->number;
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if (! list_empty(&(ctrlr->running))) {
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if (!list_empty(&(ctrlr->running))) {
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/*
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* XXX We have an active DMA transfer and currently haven't
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* sorted out the mechanism for "pending" DMA transfers.
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@ -1887,7 +1865,7 @@ int tsi148_dma_list_exec(struct vme_dma_list *list)
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int tsi148_dma_list_empty(struct vme_dma_list *list)
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||||
{
|
||||
struct list_head *pos, *temp;
|
||||
struct tsi148_dma_entry *entry;
|
||||
struct tsi148_dma_entry *entry;
|
||||
|
||||
/* detach and free each entry */
|
||||
list_for_each_safe(pos, temp, &(list->entries)) {
|
||||
@ -1896,7 +1874,7 @@ int tsi148_dma_list_empty(struct vme_dma_list *list)
|
||||
kfree(entry);
|
||||
}
|
||||
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1992,18 +1970,18 @@ int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
|
||||
if (lm_ctl & TSI148_LCSR_LMAT_EN)
|
||||
enabled = 1;
|
||||
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) {
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
|
||||
*aspace |= VME_A16;
|
||||
}
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) {
|
||||
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
|
||||
*aspace |= VME_A24;
|
||||
}
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) {
|
||||
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
|
||||
*aspace |= VME_A32;
|
||||
}
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) {
|
||||
|
||||
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
|
||||
*aspace |= VME_A64;
|
||||
}
|
||||
|
||||
|
||||
if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
|
||||
*cycle |= VME_SUPER;
|
||||
@ -2121,7 +2099,7 @@ int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
|
||||
*/
|
||||
int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
|
||||
{
|
||||
u32 slot = 0;
|
||||
u32 slot = 0;
|
||||
struct tsi148_driver *bridge;
|
||||
|
||||
bridge = tsi148_bridge->driver_priv;
|
||||
@ -2203,7 +2181,7 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
|
||||
* over the CR/CSR registers. We read from here to safely flush
|
||||
* through VME writes.
|
||||
*/
|
||||
if(err_chk) {
|
||||
if (err_chk) {
|
||||
retval = tsi148_master_set(bridge->flush_image, 1,
|
||||
(vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
|
||||
VME_D16);
|
||||
@ -2252,8 +2230,7 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
/* If we want to support more than one of each bridge, we need to
|
||||
* dynamically generate this so we get one per device
|
||||
*/
|
||||
tsi148_bridge = (struct vme_bridge *)kmalloc(sizeof(struct vme_bridge),
|
||||
GFP_KERNEL);
|
||||
tsi148_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);
|
||||
if (tsi148_bridge == NULL) {
|
||||
dev_err(&pdev->dev, "Failed to allocate memory for device "
|
||||
"structure\n");
|
||||
@ -2329,7 +2306,7 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
* hence have one less master window resource available.
|
||||
*/
|
||||
master_num = TSI148_MAX_MASTER;
|
||||
if(err_chk){
|
||||
if (err_chk) {
|
||||
master_num--;
|
||||
|
||||
tsi148_device->flush_image = (struct vme_master_resource *)
|
||||
@ -2359,8 +2336,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
/* Add master windows to list */
|
||||
INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
|
||||
for (i = 0; i < master_num; i++) {
|
||||
master_image = (struct vme_master_resource *)kmalloc(
|
||||
sizeof(struct vme_master_resource), GFP_KERNEL);
|
||||
master_image = kmalloc(sizeof(struct vme_master_resource),
|
||||
GFP_KERNEL);
|
||||
if (master_image == NULL) {
|
||||
dev_err(&pdev->dev, "Failed to allocate memory for "
|
||||
"master resource structure\n");
|
||||
@ -2388,8 +2365,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
/* Add slave windows to list */
|
||||
INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
|
||||
for (i = 0; i < TSI148_MAX_SLAVE; i++) {
|
||||
slave_image = (struct vme_slave_resource *)kmalloc(
|
||||
sizeof(struct vme_slave_resource), GFP_KERNEL);
|
||||
slave_image = kmalloc(sizeof(struct vme_slave_resource),
|
||||
GFP_KERNEL);
|
||||
if (slave_image == NULL) {
|
||||
dev_err(&pdev->dev, "Failed to allocate memory for "
|
||||
"slave resource structure\n");
|
||||
@ -2414,8 +2391,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
/* Add dma engines to list */
|
||||
INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
|
||||
for (i = 0; i < TSI148_MAX_DMA; i++) {
|
||||
dma_ctrlr = (struct vme_dma_resource *)kmalloc(
|
||||
sizeof(struct vme_dma_resource), GFP_KERNEL);
|
||||
dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
|
||||
GFP_KERNEL);
|
||||
if (dma_ctrlr == NULL) {
|
||||
dev_err(&pdev->dev, "Failed to allocate memory for "
|
||||
"dma resource structure\n");
|
||||
@ -2472,7 +2449,7 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
|
||||
data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
|
||||
dev_info(&pdev->dev, "Board is%s the VME system controller\n",
|
||||
(data & TSI148_LCSR_VSTAT_SCONS)? "" : " not");
|
||||
(data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
|
||||
if (!geoid)
|
||||
dev_info(&pdev->dev, "VME geographical address is %d\n",
|
||||
data & TSI148_LCSR_VSTAT_GA_M);
|
||||
@ -2531,7 +2508,8 @@ err_slave:
|
||||
err_master:
|
||||
/* resources are stored in link list */
|
||||
list_for_each(pos, &(tsi148_bridge->master_resources)) {
|
||||
master_image = list_entry(pos, struct vme_master_resource, list);
|
||||
master_image = list_entry(pos, struct vme_master_resource,
|
||||
list);
|
||||
list_del(pos);
|
||||
kfree(master_image);
|
||||
}
|
||||
|
||||
@ -579,7 +579,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
|
||||
/*
|
||||
* Memory Base Address Lower Reg (CRG + $010)
|
||||
*/
|
||||
#define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */
|
||||
#define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */
|
||||
#define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */
|
||||
#define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */
|
||||
#define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */
|
||||
@ -615,7 +615,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
|
||||
*/
|
||||
#define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Recieved Split Comp Error */
|
||||
#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
|
||||
#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans */
|
||||
#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans
|
||||
*/
|
||||
#define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
|
||||
#define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */
|
||||
#define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */
|
||||
@ -703,7 +704,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
|
||||
|
||||
#define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */
|
||||
|
||||
#define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask */
|
||||
#define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask
|
||||
*/
|
||||
#define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */
|
||||
#define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */
|
||||
#define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */
|
||||
@ -733,14 +735,16 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
|
||||
#define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */
|
||||
#define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */
|
||||
|
||||
#define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask */
|
||||
#define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask
|
||||
*/
|
||||
#define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */
|
||||
#define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */
|
||||
#define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */
|
||||
#define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */
|
||||
|
||||
#define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */
|
||||
#define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask */
|
||||
#define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask
|
||||
*/
|
||||
|
||||
/*
|
||||
* VMEbus Control Register CRG+$238
|
||||
@ -762,7 +766,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
|
||||
#define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24) /* 16384 VCLKS */
|
||||
#define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24) /* 32768 VCLKS */
|
||||
|
||||
#define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy */
|
||||
#define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy
|
||||
*/
|
||||
|
||||
#define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */
|
||||
#define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */
|
||||
@ -773,7 +778,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
|
||||
#define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */
|
||||
#define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */
|
||||
|
||||
#define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask */
|
||||
#define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask
|
||||
*/
|
||||
#define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
|
||||
#define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */
|
||||
#define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
|
||||
@ -794,7 +800,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
|
||||
#define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */
|
||||
#define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */
|
||||
#define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */
|
||||
#define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */
|
||||
#define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */
|
||||
|
||||
/*
|
||||
* PCI Configuration Status Register CRG+$240
|
||||
@ -1341,7 +1347,7 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
|
||||
* DMA Next Link Address Lower
|
||||
*/
|
||||
#define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6) /* Address Mask */
|
||||
#define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */
|
||||
#define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */
|
||||
|
||||
/*
|
||||
* DMA 2eSST Broadcast Select
|
||||
@ -1371,7 +1377,7 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
|
||||
#define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */
|
||||
|
||||
#define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */
|
||||
#define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */
|
||||
#define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */
|
||||
|
||||
/*
|
||||
* CR/CSR Register Group
|
||||
|
||||
Loading…
Reference in New Issue
Block a user