can: ctucanfd: CTU CAN FD open-source IP core - PCI bus support.
PCI bus adaptation for CTU CAN FD open-source IP core. The project providing FPGA design for Intel EP4CGX15 based DB4CGX15 PCIe board with PiKRON.com designed transceiver riser shield is available at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd . Link: https://lore.kernel.org/all/a81333e206a9bcf9434797f6f54d8664775542e2.1647904780.git.pisa@cmp.felk.cvut.cz Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Martin Jerabek <martin.jerabek01@gmail.com> Signed-off-by: Ondrej Ille <ondrej.ille@gmail.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Pavel Pisa
Marc Kleine-Budde
parent
2dcb8e8782
commit
792a5b678e
@ -10,3 +10,13 @@ config CAN_CTUCANFD
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from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
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on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
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Guidepost CTU FEE CAN bus projects page https://canbus.pages.fel.cvut.cz/ .
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config CAN_CTUCANFD_PCI
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tristate "CTU CAN-FD IP core PCI/PCIe driver"
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depends on CAN_CTUCANFD
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depends on PCI
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help
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This driver adds PCI/PCIe support for CTU CAN-FD IP core.
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The project providing FPGA design for Intel EP4CGX15 based DB4CGX15
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PCIe board with PiKRON.com designed transceiver riser shield is available
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at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd .
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@ -5,3 +5,5 @@
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obj-$(CONFIG_CAN_CTUCANFD) := ctucanfd.o
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ctucanfd-y := ctucanfd_base.o
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obj-$(CONFIG_CAN_CTUCANFD_PCI) += ctucanfd_pci.o
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304
drivers/net/can/ctucanfd/ctucanfd_pci.c
Normal file
304
drivers/net/can/ctucanfd/ctucanfd_pci.c
Normal file
@ -0,0 +1,304 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*******************************************************************************
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*
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* CTU CAN FD IP Core
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*
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Project advisors:
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* Jiri Novak <jnovak@fel.cvut.cz>
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* Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Department of Measurement (http://meas.fel.cvut.cz/)
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* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
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* Czech Technical University (http://www.cvut.cz/)
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******************************************************************************/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "ctucanfd.h"
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#ifndef PCI_DEVICE_DATA
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#define PCI_DEVICE_DATA(vend, dev, data) \
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.vendor = PCI_VENDOR_ID_##vend, \
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.device = PCI_DEVICE_ID_##vend##_##dev, \
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.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
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.driver_data = (kernel_ulong_t)(data)
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#endif
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#ifndef PCI_VENDOR_ID_TEDIA
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#define PCI_VENDOR_ID_TEDIA 0x1760
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#endif
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#ifndef PCI_DEVICE_ID_TEDIA_CTUCAN_VER21
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#define PCI_DEVICE_ID_TEDIA_CTUCAN_VER21 0xff00
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#endif
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#define CTUCAN_BAR0_CTUCAN_ID 0x0000
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#define CTUCAN_BAR0_CRA_BASE 0x4000
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#define CYCLONE_IV_CRA_A2P_IE (0x0050)
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#define CTUCAN_WITHOUT_CTUCAN_ID 0
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#define CTUCAN_WITH_CTUCAN_ID 1
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static bool use_msi = true;
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module_param(use_msi, bool, 0444);
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MODULE_PARM_DESC(use_msi, "PCIe implementation use MSI interrupts. Default: 1 (yes)");
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static bool pci_use_second = true;
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module_param(pci_use_second, bool, 0444);
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MODULE_PARM_DESC(pci_use_second, "Use the second CAN core on PCIe card. Default: 1 (yes)");
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struct ctucan_pci_board_data {
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void __iomem *bar0_base;
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void __iomem *cra_base;
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void __iomem *bar1_base;
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struct list_head ndev_list_head;
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int use_msi;
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};
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static struct ctucan_pci_board_data *ctucan_pci_get_bdata(struct pci_dev *pdev)
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{
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return (struct ctucan_pci_board_data *)pci_get_drvdata(pdev);
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}
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static void ctucan_pci_set_drvdata(struct device *dev,
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struct net_device *ndev)
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{
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struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
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struct ctucan_priv *priv = netdev_priv(ndev);
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struct ctucan_pci_board_data *bdata = ctucan_pci_get_bdata(pdev);
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list_add(&priv->peers_on_pdev, &bdata->ndev_list_head);
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priv->irq_flags = IRQF_SHARED;
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}
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/**
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* ctucan_pci_probe - PCI registration call
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* @pdev: Handle to the pci device structure
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* @ent: Pointer to the entry from ctucan_pci_tbl
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*
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* This function does all the memory allocation and registration for the CAN
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* device.
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*
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* Return: 0 on success and failure value on error
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*/
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static int ctucan_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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unsigned long driver_data = ent->driver_data;
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struct ctucan_pci_board_data *bdata;
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void __iomem *addr;
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void __iomem *cra_addr;
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void __iomem *bar0_base;
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u32 cra_a2p_ie;
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u32 ctucan_id = 0;
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int ret;
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unsigned int ntxbufs;
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unsigned int num_cores = 1;
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unsigned int core_i = 0;
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int irq;
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int msi_ok = 0;
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(dev, "pci_enable_device FAILED\n");
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goto err;
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}
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ret = pci_request_regions(pdev, KBUILD_MODNAME);
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if (ret) {
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dev_err(dev, "pci_request_regions FAILED\n");
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goto err_disable_device;
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}
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if (use_msi) {
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ret = pci_enable_msi(pdev);
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if (!ret) {
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dev_info(dev, "MSI enabled\n");
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pci_set_master(pdev);
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msi_ok = 1;
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}
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}
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dev_info(dev, "ctucan BAR0 0x%08llx 0x%08llx\n",
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(long long)pci_resource_start(pdev, 0),
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(long long)pci_resource_len(pdev, 0));
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dev_info(dev, "ctucan BAR1 0x%08llx 0x%08llx\n",
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(long long)pci_resource_start(pdev, 1),
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(long long)pci_resource_len(pdev, 1));
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addr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
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if (!addr) {
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dev_err(dev, "PCI BAR 1 cannot be mapped\n");
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ret = -ENOMEM;
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goto err_release_regions;
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}
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/* Cyclone IV PCI Express Control Registers Area */
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bar0_base = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
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if (!bar0_base) {
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dev_err(dev, "PCI BAR 0 cannot be mapped\n");
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ret = -EIO;
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goto err_pci_iounmap_bar1;
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}
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if (driver_data == CTUCAN_WITHOUT_CTUCAN_ID) {
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cra_addr = bar0_base;
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num_cores = 2;
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} else {
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cra_addr = bar0_base + CTUCAN_BAR0_CRA_BASE;
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ctucan_id = ioread32(bar0_base + CTUCAN_BAR0_CTUCAN_ID);
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dev_info(dev, "ctucan_id 0x%08lx\n", (unsigned long)ctucan_id);
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num_cores = ctucan_id & 0xf;
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}
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irq = pdev->irq;
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ntxbufs = 4;
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bdata = kzalloc(sizeof(*bdata), GFP_KERNEL);
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if (!bdata) {
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ret = -ENOMEM;
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goto err_pci_iounmap_bar0;
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}
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INIT_LIST_HEAD(&bdata->ndev_list_head);
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bdata->bar0_base = bar0_base;
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bdata->cra_base = cra_addr;
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bdata->bar1_base = addr;
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bdata->use_msi = msi_ok;
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pci_set_drvdata(pdev, bdata);
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ret = ctucan_probe_common(dev, addr, irq, ntxbufs, 100000000,
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0, ctucan_pci_set_drvdata);
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if (ret < 0)
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goto err_free_board;
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core_i++;
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while (pci_use_second && (core_i < num_cores)) {
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addr += 0x4000;
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ret = ctucan_probe_common(dev, addr, irq, ntxbufs, 100000000,
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0, ctucan_pci_set_drvdata);
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if (ret < 0) {
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dev_info(dev, "CTU CAN FD core %d initialization failed\n",
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core_i);
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break;
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}
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core_i++;
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}
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/* enable interrupt in
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* Avalon-MM to PCI Express Interrupt Enable Register
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*/
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cra_a2p_ie = ioread32(cra_addr + CYCLONE_IV_CRA_A2P_IE);
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dev_info(dev, "cra_a2p_ie 0x%08x\n", cra_a2p_ie);
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cra_a2p_ie |= 1;
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iowrite32(cra_a2p_ie, cra_addr + CYCLONE_IV_CRA_A2P_IE);
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cra_a2p_ie = ioread32(cra_addr + CYCLONE_IV_CRA_A2P_IE);
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dev_info(dev, "cra_a2p_ie 0x%08x\n", cra_a2p_ie);
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return 0;
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err_free_board:
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pci_set_drvdata(pdev, NULL);
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kfree(bdata);
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err_pci_iounmap_bar0:
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pci_iounmap(pdev, cra_addr);
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err_pci_iounmap_bar1:
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pci_iounmap(pdev, addr);
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err_release_regions:
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if (msi_ok) {
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pci_disable_msi(pdev);
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pci_clear_master(pdev);
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}
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pci_release_regions(pdev);
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err_disable_device:
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pci_disable_device(pdev);
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err:
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return ret;
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}
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/**
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* ctucan_pci_remove - Unregister the device after releasing the resources
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* @pdev: Handle to the pci device structure
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*
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* This function frees all the resources allocated to the device.
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* Return: 0 always
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*/
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static void ctucan_pci_remove(struct pci_dev *pdev)
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{
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struct net_device *ndev;
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struct ctucan_priv *priv = NULL;
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struct ctucan_pci_board_data *bdata = ctucan_pci_get_bdata(pdev);
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dev_dbg(&pdev->dev, "ctucan_remove");
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if (!bdata) {
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dev_err(&pdev->dev, "%s: no list of devices\n", __func__);
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return;
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}
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/* disable interrupt in
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* Avalon-MM to PCI Express Interrupt Enable Register
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*/
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if (bdata->cra_base)
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iowrite32(0, bdata->cra_base + CYCLONE_IV_CRA_A2P_IE);
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while ((priv = list_first_entry_or_null(&bdata->ndev_list_head, struct ctucan_priv,
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peers_on_pdev)) != NULL) {
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ndev = priv->can.dev;
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unregister_candev(ndev);
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netif_napi_del(&priv->napi);
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list_del_init(&priv->peers_on_pdev);
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free_candev(ndev);
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}
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pci_iounmap(pdev, bdata->bar1_base);
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if (bdata->use_msi) {
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pci_disable_msi(pdev);
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pci_clear_master(pdev);
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}
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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pci_iounmap(pdev, bdata->bar0_base);
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pci_set_drvdata(pdev, NULL);
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kfree(bdata);
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}
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static SIMPLE_DEV_PM_OPS(ctucan_pci_pm_ops, ctucan_suspend, ctucan_resume);
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static const struct pci_device_id ctucan_pci_tbl[] = {
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{PCI_DEVICE_DATA(TEDIA, CTUCAN_VER21,
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CTUCAN_WITH_CTUCAN_ID)},
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{},
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};
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static struct pci_driver ctucan_pci_driver = {
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.name = KBUILD_MODNAME,
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.id_table = ctucan_pci_tbl,
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.probe = ctucan_pci_probe,
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.remove = ctucan_pci_remove,
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.driver.pm = &ctucan_pci_pm_ops,
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};
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module_pci_driver(ctucan_pci_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Pavel Pisa <pisa@cmp.felk.cvut.cz>");
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MODULE_DESCRIPTION("CTU CAN FD for PCI bus");
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