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drm/nouveau/pm: some more delays for ddr3 reclocking

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These numbers from the binary driver's daemon scripts, and fix the transition
to perflvl 3 on my T510.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-02-06 16:20:30 +10:00
parent 9d6ba0b58c
commit 78c2018658
2 changed files with 4 additions and 0 deletions
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3
drivers/gpu/drm/nouveau/nouveau_mem.c
View File

@ -978,6 +978,8 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
break;
case NV_MEM_TYPE_DDR3:
tDLLK = 12000;
tCKSRE = 2000;
tXS = 1000;
mr1_dlloff = 0x00000001;
break;
case NV_MEM_TYPE_GDDR3:
@ -1024,6 +1026,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
exec->refresh_self(exec, false);
exec->refresh_auto(exec, true);
exec->wait(exec, tXS);
exec->wait(exec, tXS);
/* update MRs */
if (mr[2] != info->mr[2]) {

1
drivers/gpu/drm/nouveau/nva3_pm.c
View File

@ -344,6 +344,7 @@ mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
static void
mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
{
volatile u32 post = nv_rd32(exec->dev, 0); (void)post;
udelay((nsec + 500) / 1000);
}