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crypto: atmel-aes - Fix counter overflow in CTR mode

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32 bit counter is not supported by neither of our AES IPs, all implement
a 16 bit block counter. Drop the 32 bit block counter logic.

Fixes: fcac83656a ("crypto: atmel-aes - fix the counter overflow in CTR mode")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Tudor Ambarus 2019-12-05 09:54:01 +00:00 committed by Herbert Xu
parent c65d123742
commit 781a08d974
1 changed files with 10 additions and 23 deletions
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33
drivers/crypto/atmel-aes.c
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@ -88,7 +88,6 @@
struct atmel_aes_caps { struct atmel_aes_caps {
bool has_dualbuff; bool has_dualbuff;
bool has_cfb64; bool has_cfb64;
bool has_ctr32;
bool has_gcm; bool has_gcm;
bool has_xts; bool has_xts;
bool has_authenc; bool has_authenc;
@ -1018,8 +1017,9 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
struct skcipher_request *req = skcipher_request_cast(dd->areq); struct skcipher_request *req = skcipher_request_cast(dd->areq);
struct scatterlist *src, *dst; struct scatterlist *src, *dst;
u32 ctr, blocks;
size_t datalen; size_t datalen;
u32 ctr;
u16 blocks, start, end;
bool use_dma, fragmented = false; bool use_dma, fragmented = false;
/* Check for transfer completion. */ /* Check for transfer completion. */
@ -1031,27 +1031,17 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
datalen = req->cryptlen - ctx->offset; datalen = req->cryptlen - ctx->offset;
blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE); blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
ctr = be32_to_cpu(ctx->iv[3]); ctr = be32_to_cpu(ctx->iv[3]);
if (dd->caps.has_ctr32) {
/* Check 32bit counter overflow. */
u32 start = ctr;
u32 end = start + blocks - 1;
if (end < start) { /* Check 16bit counter overflow. */
ctr |= 0xffffffff; start = ctr & 0xffff;
datalen = AES_BLOCK_SIZE * -start; end = start + blocks - 1;
fragmented = true;
}
} else {
/* Check 16bit counter overflow. */
u16 start = ctr & 0xffff;
u16 end = start + (u16)blocks - 1;
if (blocks >> 16 || end < start) { if (blocks >> 16 || end < start) {
ctr |= 0xffff; ctr |= 0xffff;
datalen = AES_BLOCK_SIZE * (0x10000-start); datalen = AES_BLOCK_SIZE * (0x10000 - start);
fragmented = true; fragmented = true;
}
} }
use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD); use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
/* Jump to offset. */ /* Jump to offset. */
@ -2521,7 +2511,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
{ {
dd->caps.has_dualbuff = 0; dd->caps.has_dualbuff = 0;
dd->caps.has_cfb64 = 0; dd->caps.has_cfb64 = 0;
dd->caps.has_ctr32 = 0;
dd->caps.has_gcm = 0; dd->caps.has_gcm = 0;
dd->caps.has_xts = 0; dd->caps.has_xts = 0;
dd->caps.has_authenc = 0; dd->caps.has_authenc = 0;
@ -2532,7 +2521,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
case 0x500: case 0x500:
dd->caps.has_dualbuff = 1; dd->caps.has_dualbuff = 1;
dd->caps.has_cfb64 = 1; dd->caps.has_cfb64 = 1;
dd->caps.has_ctr32 = 1;
dd->caps.has_gcm = 1; dd->caps.has_gcm = 1;
dd->caps.has_xts = 1; dd->caps.has_xts = 1;
dd->caps.has_authenc = 1; dd->caps.has_authenc = 1;
@ -2541,7 +2529,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
case 0x200: case 0x200:
dd->caps.has_dualbuff = 1; dd->caps.has_dualbuff = 1;
dd->caps.has_cfb64 = 1; dd->caps.has_cfb64 = 1;
dd->caps.has_ctr32 = 1;
dd->caps.has_gcm = 1; dd->caps.has_gcm = 1;
dd->caps.max_burst_size = 4; dd->caps.max_burst_size = 4;
break; break;