ARM: dts: Zynq DT changes for v5.12-v2
- Add Ebang board support - Add missing zturn boards in dt binding - And convert Zynq QSPI binding -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYCUVcgAKCRDKSWXLKUoM IZVWAKCM5e+z5R7MwgG/MUSnwhZ3GmjKsACbB3bnWgN/h2mywCGBWvyuho+FlYQ= =h0Yg -----END PGP SIGNATURE----- Merge tag 'zynq-dt-for-v5.12-v2' of https://github.com/Xilinx/linux-xlnx into arm/dt ARM: dts: Zynq DT changes for v5.12-v2 - Add Ebang board support - Add missing zturn boards in dt binding - And convert Zynq QSPI binding * tag 'zynq-dt-for-v5.12-v2' of https://github.com/Xilinx/linux-xlnx: dt-bindings: spi: zynq: Convert Zynq QSPI binding to yaml dt-bindings: arm: xilinx: Add missing Zturn boards ARM: dts: ebaz4205: add pinctrl entries for switches ARM: dts: add Ebang EBAZ4205 device tree dt-bindings: arm: add Ebang EBAZ4205 board dt-bindings: add ebang vendor prefix Link: https://lore.kernel.org/r/19e0e0c9-1bed-bba5-6c80-6903937b3d96@xilinx.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann
commit
7815552728
@ -22,6 +22,9 @@ properties:
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- adapteva,parallella
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- digilent,zynq-zybo
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- digilent,zynq-zybo-z7
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- ebang,ebaz4205
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- myir,zynq-zturn-v5
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- myir,zynq-zturn
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- xlnx,zynq-cc108
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- xlnx,zynq-zc702
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- xlnx,zynq-zc706
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@ -1,25 +0,0 @@
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Xilinx Zynq QSPI controller Device Tree Bindings
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-------------------------------------------------------------------
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Required properties:
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- compatible : Should be "xlnx,zynq-qspi-1.0".
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- reg : Physical base address and size of QSPI registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- clock-names : List of input clock names - "ref_clk", "pclk"
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(See clock bindings for details).
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- clocks : Clock phandles (see clock bindings for details).
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Optional properties:
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- num-cs : Number of chip selects used.
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Example:
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qspi: spi@e000d000 {
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compatible = "xlnx,zynq-qspi-1.0";
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reg = <0xe000d000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <0 19 4>;
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clock-names = "ref_clk", "pclk";
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clocks = <&clkc 10>, <&clkc 43>;
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num-cs = <1>;
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};
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59
Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
Normal file
59
Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
Normal file
@ -0,0 +1,59 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Zynq QSPI controller
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description:
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The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
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memory devices.
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allOf:
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- $ref: "spi-controller.yaml#"
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maintainers:
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- Michal Simek <michal.simek@xilinx.com>
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# Everything else is described in the common file
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properties:
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compatible:
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const: xlnx,zynq-qspi-1.0
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: reference clock
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- description: peripheral clock
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clock-names:
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items:
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- const: ref_clk
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- const: pclk
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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spi@e000d000 {
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compatible = "xlnx,zynq-qspi-1.0";
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reg = <0xe000d000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <0 19 4>;
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clock-names = "ref_clk", "pclk";
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clocks = <&clkc 10>, <&clkc 43>;
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num-cs = <1>;
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};
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@ -313,6 +313,8 @@ patternProperties:
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description: Dyna-Image
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"^ea,.*":
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description: Embedded Artists AB
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"^ebang,.*":
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description: Zhejiang Ebang Communication Co., Ltd
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"^ebs-systart,.*":
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description: EBS-SYSTART GmbH
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"^ebv,.*":
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@ -2768,6 +2768,7 @@ W: http://wiki.xilinx.com
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T: git https://github.com/Xilinx/linux-xlnx.git
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F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
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F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
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F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
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F: arch/arm/mach-zynq/
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F: drivers/block/xsysace.c
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F: drivers/clocksource/timer-cadence-ttc.c
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@ -1322,6 +1322,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
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wm8850-w70v2.dtb
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dtb-$(CONFIG_ARCH_ZYNQ) += \
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zynq-cc108.dtb \
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zynq-ebaz4205.dtb \
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zynq-microzed.dtb \
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zynq-parallella.dtb \
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zynq-zc702.dtb \
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132
arch/arm/boot/dts/zynq-ebaz4205.dts
Normal file
132
arch/arm/boot/dts/zynq-ebaz4205.dts
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@ -0,0 +1,132 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Michael Walle <michael@walle.cc>
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*/
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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model = "Ebang EBAZ4205";
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compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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serial0 = &uart1;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>;
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fclk-enable = <8>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "mii";
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phy-handle = <&phy>;
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/* PHY clock */
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assigned-clocks = <&clkc 18>;
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assigned-clock-rates = <25000000>;
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phy: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio0_default>;
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};
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&pinctrl0 {
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pinctrl_gpio0_default: gpio0-default {
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mux {
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groups = "gpio0_20_grp", "gpio0_32_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_20_grp", "gpio0_32_grp";
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io-standard = <3>;
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slew-rate = <0>;
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};
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conf-pull-up {
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pins = "MIO20", "MIO32";
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bias-disable;
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};
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};
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pinctrl_sdhci0_default: sdhci0-default {
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mux {
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groups = "sdio0_2_grp";
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function = "sdio0";
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};
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conf {
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groups = "sdio0_2_grp";
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io-standard = <3>;
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slew-rate = <0>;
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bias-disable;
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};
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mux-cd {
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groups = "gpio0_34_grp";
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function = "sdio0_cd";
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};
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conf-cd {
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groups = "gpio0_34_grp";
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io-standard = <3>;
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slew-rate = <0>;
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bias-high-impedance;
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bias-pull-up;
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};
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};
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_4_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_4_grp";
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io-standard = <3>;
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slew-rate = <0>;
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};
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conf-rx {
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pins = "MIO25";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO24";
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bias-disable;
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};
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};
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};
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&sdhci0 {
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status = "okay";
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0_default>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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