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drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric

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Similar to earlier conversions, eliminate the implicit dev_priv by
introducing some helpers which take the engine parameter (since the
register itself is per engine).

v2:
 * Always use parentheses in macro arguments.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190607101535.767-1-tvrtko.ursulin@linux.intel.com
This commit is contained in:
Tvrtko Ursulin 2019-06-07 11:15:35 +01:00
parent 7c53c48d01
commit 77a302e043
4 changed files with 22 additions and 6 deletions
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18
drivers/gpu/drm/i915/gt/intel_engine.h
View File

@ -68,6 +68,24 @@ struct drm_printer;
#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
#define GEN6_RING_FAULT_REG_READ(engine__) \
intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
({ \
u32 __val; \
\
__val = intel_uncore_read((engine__)->uncore, \
RING_FAULT_REG(engine__)); \
__val &= ~(clear__); \
__val |= (set__); \
intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
__val); \
})
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
*/

6
drivers/gpu/drm/i915/gt/intel_reset.c
View File

@ -1195,10 +1195,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
enum intel_engine_id id;
for_each_engine_masked(engine, i915, engine_mask, id) {
rmw_clear(uncore,
RING_FAULT_REG(engine), RING_FAULT_VALID);
intel_uncore_posting_read(uncore,
RING_FAULT_REG(engine));
GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
GEN6_RING_FAULT_REG_POSTING_READ(engine);
}
}
}

2
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -2306,7 +2306,7 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv)
u32 fault;
for_each_engine(engine, dev_priv, id) {
fault = I915_READ(RING_FAULT_REG(engine));
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
"\tAddr: 0x%08lx\n"

2
drivers/gpu/drm/i915/i915_gpu_error.c
View File

@ -1149,7 +1149,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else
ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
}
if (INTEL_GEN(dev_priv) >= 4) {