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ARM: dts: Renesas R9A06G032 base device tree file

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This adds the Renesas R9A06G032 bare bone support.

This currently only handles the SYSCTRL block note,
generic parts (gic, architected timer) and a UART.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated MAINTAINERS file
[simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Michel Pollet 2018-06-14 11:56:32 +01:00 committed by Simon Horman
parent cdbfaf640a
commit 769d7248a7
2 changed files with 114 additions and 0 deletions
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1
MAINTAINERS
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@ -1969,6 +1969,7 @@ S: Supported
F: arch/arm/boot/dts/emev2*
F: arch/arm/boot/dts/r7s*
F: arch/arm/boot/dts/r8a*
F: arch/arm/boot/dts/r9a*
F: arch/arm/boot/dts/sh*
F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S

113
arch/arm/boot/dts/r9a06g032.dtsi Normal file
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@ -0,0 +1,113 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r9a06g032";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clocks = <&sysctrl 84>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <1>;
clocks = <&sysctrl 84>;
};
};
ext_jtag_clk: extjtagclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ext_mclk: extmclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
};
ext_rgmii_ref: extrgmiiref {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ext_rtc_clk: extrtcclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges;
sysctrl: system-controller@4000c000 {
compatible = "renesas,r9a06g032-sysctrl";
reg = <0x4000c000 0x1000>;
status = "okay";
#clock-cells = <1>;
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
};
uart0: serial@40060000 {
compatible = "snps,dw-apb-uart";
reg = <0x40060000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl 146>;
clock-names = "baudclk";
status = "disabled";
};
gic: gic@44101000 {
compatible = "arm,cortex-a7-gic", "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x44101000 0x1000>, /* Distributer */
<0x44102000 0x2000>, /* CPU interface */
<0x44104000 0x2000>, /* Virt interface control */
<0x44106000 0x2000>; /* Virt CPU interface */
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
};
timer {
compatible = "arm,cortex-a7-timer",
"arm,armv7-timer";
interrupt-parent = <&gic>;
arm,cpu-registers-not-fw-configured;
always-on;
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};