ARM: proc: add proc info for Cortex-A15MP using classic page tables
Multicore implementations of the Cortex-A15 require bit 6 of the auxiliary control register to be set in order for cache and TLB maintenance operations to be broadcast between CPUs. This patch adds a new proc_info structure for Cortex-A15, which enables the SMP bit during setup and includes the new HWCAP for integer division. Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -280,12 +280,18 @@ cpu_resume_l1_flags:
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*/
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__v7_ca5mp_setup:
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__v7_ca9mp_setup:
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mov r10, #(1 << 0) @ TLB ops broadcasting
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b 1f
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__v7_ca15mp_setup:
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mov r10, #0
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1:
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
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ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
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tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
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orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
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mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
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orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
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orreq r0, r0, r10 @ Enable CPU-specific SMP bits
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mcreq p15, 0, r0, c1, c0, 1
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#endif
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__v7_setup:
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adr r12, __v7_setup_stack @ the local stack
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@ -464,6 +470,16 @@ __v7_ca9mp_proc_info:
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__v7_proc __v7_ca9mp_setup
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.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
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/*
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* ARM Ltd. Cortex A15 processor.
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*/
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.type __v7_ca15mp_proc_info, #object
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__v7_ca15mp_proc_info:
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.long 0x410fc0f0
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.long 0xff0ffff0
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__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
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.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
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/*
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* Match any ARMv7 processor core.
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*/
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