drm/amd/display: Update hubbub description comment
Description for DCHUBBUB_TEST_DEBUG_DATA is changed to avoid any future confusions. Signed-off-by: Peikang Zhang <peikang.zhang@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher
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@@ -147,8 +147,9 @@ bool hubbub1_verify_allow_pstate_change_high(
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forced_pstate_allow = false;
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forced_pstate_allow = false;
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}
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}
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/* RV2:
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/* The following table only applies to DCN1 and DCN2,
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* dchubbubdebugind, at: 0xB
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* for newer DCNs, need to consult with HW IP folks to read RTL
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* HUBBUB:DCHUBBUB_TEST_ARB_DEBUG10 DCHUBBUBDEBUGIND:0xB
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* description
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* description
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* 0: Pipe0 Plane0 Allow Pstate Change
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* 0: Pipe0 Plane0 Allow Pstate Change
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* 1: Pipe0 Plane1 Allow Pstate Change
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* 1: Pipe0 Plane1 Allow Pstate Change
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@@ -181,64 +182,6 @@ bool hubbub1_verify_allow_pstate_change_high(
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* 28: WB0 Allow Pstate Change
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* 28: WB0 Allow Pstate Change
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* 29: WB1 Allow Pstate Change
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* 29: WB1 Allow Pstate Change
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* 30: Arbiter's allow_pstate_change
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* 30: Arbiter's allow_pstate_change
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* 31: SOC pstate change request"
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*/
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/*DCN2.x:
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HUBBUB:DCHUBBUB_TEST_ARB_DEBUG10 DCHUBBUBDEBUGIND:0xB
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0: Pipe0 Plane0 Allow P-state Change
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1: Pipe0 Plane1 Allow P-state Change
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2: Pipe0 Cursor0 Allow P-state Change
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3: Pipe0 Cursor1 Allow P-state Change
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4: Pipe1 Plane0 Allow P-state Change
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5: Pipe1 Plane1 Allow P-state Change
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6: Pipe1 Cursor0 Allow P-state Change
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7: Pipe1 Cursor1 Allow P-state Change
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8: Pipe2 Plane0 Allow P-state Change
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9: Pipe2 Plane1 Allow P-state Change
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10: Pipe2 Cursor0 Allow P-state Change
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11: Pipe2 Cursor1 Allow P-state Change
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12: Pipe3 Plane0 Allow P-state Change
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13: Pipe3 Plane1 Allow P-state Change
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14: Pipe3 Cursor0 Allow P-state Change
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15: Pipe3 Cursor1 Allow P-state Change
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16: Pipe4 Plane0 Allow P-state Change
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17: Pipe4 Plane1 Allow P-state Change
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18: Pipe4 Cursor0 Allow P-state Change
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19: Pipe4 Cursor1 Allow P-state Change
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20: Pipe5 Plane0 Allow P-state Change
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21: Pipe5 Plane1 Allow P-state Change
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22: Pipe5 Cursor0 Allow P-state Change
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23: Pipe5 Cursor1 Allow P-state Change
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24: Pipe6 Plane0 Allow P-state Change
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25: Pipe6 Plane1 Allow P-state Change
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26: Pipe6 Cursor0 Allow P-state Change
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27: Pipe6 Cursor1 Allow P-state Change
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28: WB0 Allow P-state Change
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29: WB1 Allow P-state Change
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30: Arbiter`s Allow P-state Change
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31: SOC P-state Change request
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*/
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/* RV1:
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* dchubbubdebugind, at: 0x7
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* description "3-0: Pipe0 cursor0 QOS
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* 7-4: Pipe1 cursor0 QOS
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* 11-8: Pipe2 cursor0 QOS
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* 15-12: Pipe3 cursor0 QOS
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* 16: Pipe0 Plane0 Allow Pstate Change
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* 17: Pipe1 Plane0 Allow Pstate Change
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* 18: Pipe2 Plane0 Allow Pstate Change
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* 19: Pipe3 Plane0 Allow Pstate Change
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* 20: Pipe0 Plane1 Allow Pstate Change
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* 21: Pipe1 Plane1 Allow Pstate Change
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* 22: Pipe2 Plane1 Allow Pstate Change
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* 23: Pipe3 Plane1 Allow Pstate Change
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* 24: Pipe0 cursor0 Allow Pstate Change
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* 25: Pipe1 cursor0 Allow Pstate Change
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* 26: Pipe2 cursor0 Allow Pstate Change
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* 27: Pipe3 cursor0 Allow Pstate Change
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* 28: WB0 Allow Pstate Change
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* 29: WB1 Allow Pstate Change
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* 30: Arbiter's allow_pstate_change
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* 31: SOC pstate change request
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* 31: SOC pstate change request
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*/
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*/
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