forked from Minki/linux
ARM: l2c: implement fixups for L2 cache controller quirks/errata
Rather than putting quirk handling in __l2c_init(), move it out to a separate function which individual implementations can specify. This helps to localise the quirks to those implementations which require them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
40266d6f41
commit
75461f5c84
@ -32,6 +32,7 @@ struct l2c_init_data {
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unsigned num_lock;
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void (*of_parse)(const struct device_node *, u32 *, u32 *);
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void (*enable)(void __iomem *, u32, unsigned);
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void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
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void (*save)(void __iomem *);
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struct outer_cache_fns outer_cache;
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};
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@ -394,9 +395,80 @@ static const struct l2c_init_data l2x0_init_fns __initconst = {
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},
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};
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/*
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* L2C-310 specific code.
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*
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* Errata:
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* 588369: PL310 R0P0->R1P0, fixed R2P0.
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* Affects: all clean+invalidate operations
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* clean and invalidate skips the invalidate step, so we need to issue
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* separate operations. We also require the above debug workaround
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* enclosing this code fragment on affected parts. On unaffected parts,
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* we must not use this workaround without the debug register writes
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* to avoid exposing a problem similar to 727915.
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*
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* 727915: PL310 R2P0->R3P0, fixed R3P1.
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* Affects: clean+invalidate by way
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* clean and invalidate by way runs in the background, and a store can
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* hit the line between the clean operation and invalidate operation,
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* resulting in the store being lost.
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*
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* 753970: PL310 R3P0, fixed R3P1.
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* Affects: sync
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* prevents merging writes after the sync operation, until another L2C
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* operation is performed (or a number of other conditions.)
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*
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* 769419: PL310 R0P0->R3P1, fixed R3P2.
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* Affects: store buffer
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* store buffer is not automatically drained.
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*/
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static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
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struct outer_cache_fns *fns)
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{
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unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK;
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const char *errata[4];
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unsigned n = 0;
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if (revision <= L310_CACHE_ID_RTL_R3P0)
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fns->set_debug = pl310_set_debug;
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if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) &&
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revision == L310_CACHE_ID_RTL_R3P0) {
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sync_reg_offset = L2X0_DUMMY_REG;
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errata[n++] = "753970";
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}
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if (IS_ENABLED(CONFIG_PL310_ERRATA_769419))
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errata[n++] = "769419";
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if (n) {
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unsigned i;
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pr_info("L2C-310 errat%s", n > 1 ? "a" : "um");
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for (i = 0; i < n; i++)
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pr_cont(" %s", errata[i]);
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pr_cont(" enabled\n");
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}
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}
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static const struct l2c_init_data l2c310_init_fns __initconst = {
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.num_lock = 8,
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.enable = l2c_enable,
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.fixup = l2c310_fixup,
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.outer_cache = {
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.inv_range = l2x0_inv_range,
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.clean_range = l2x0_clean_range,
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.flush_range = l2x0_flush_range,
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.flush_all = l2x0_flush_all,
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.disable = l2x0_disable,
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.sync = l2x0_cache_sync,
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},
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};
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static void __init __l2c_init(const struct l2c_init_data *data,
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u32 aux_val, u32 aux_mask, u32 cache_id)
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{
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struct outer_cache_fns fns;
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u32 aux;
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u32 way_size = 0;
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int ways;
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@ -423,23 +495,20 @@ static void __init __l2c_init(const struct l2c_init_data *data,
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else
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ways = 8;
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type = "L310";
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#ifdef CONFIG_PL310_ERRATA_753970
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/* Unmapped register. */
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sync_reg_offset = L2X0_DUMMY_REG;
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#endif
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break;
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case L2X0_CACHE_ID_PART_L210:
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ways = (aux >> 13) & 0xf;
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type = "L210";
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break;
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case AURORA_CACHE_ID:
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sync_reg_offset = AURORA_SYNC_REG;
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ways = (aux >> 13) & 0xf;
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ways = 2 << ((ways + 1) >> 2);
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way_size_shift = AURORA_WAY_SIZE_SHIFT;
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type = "Aurora";
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break;
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default:
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/* Assume unknown chips have 8 ways */
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ways = 8;
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@ -457,6 +526,10 @@ static void __init __l2c_init(const struct l2c_init_data *data,
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l2x0_size = ways * way_size * SZ_1K;
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fns = data->outer_cache;
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if (data->fixup)
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data->fixup(l2x0_base, cache_id, &fns);
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/*
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* Check if l2x0 controller is already enabled. If we are booting
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* in non-secure mode accessing the below registers will fault.
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@ -470,11 +543,7 @@ static void __init __l2c_init(const struct l2c_init_data *data,
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/* Save the value for resuming. */
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l2x0_saved_regs.aux_ctrl = aux;
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outer_cache = data->outer_cache;
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if ((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310 &&
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(cache_id & L2X0_CACHE_ID_RTL_MASK) <= L310_CACHE_ID_RTL_R3P0)
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outer_cache.set_debug = pl310_set_debug;
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outer_cache = fns;
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pr_info("%s cache controller enabled\n", type);
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pr_info("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d kB\n",
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@ -483,13 +552,24 @@ static void __init __l2c_init(const struct l2c_init_data *data,
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void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
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{
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const struct l2c_init_data *data;
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u32 cache_id;
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l2x0_base = base;
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cache_id = readl_relaxed(base + L2X0_CACHE_ID);
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__l2c_init(&l2x0_init_fns, aux_val, aux_mask, cache_id);
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switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
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default:
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data = &l2x0_init_fns;
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break;
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case L2X0_CACHE_ID_PART_L310:
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data = &l2c310_init_fns;
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break;
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}
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__l2c_init(data, aux_val, aux_mask, cache_id);
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}
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#ifdef CONFIG_OF
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@ -659,6 +739,7 @@ static const struct l2c_init_data of_pl310_data __initconst = {
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.num_lock = 8,
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.of_parse = pl310_of_parse,
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.enable = l2c_enable,
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.fixup = l2c310_fixup,
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.save = pl310_save,
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.outer_cache = {
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.inv_range = l2x0_inv_range,
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@ -802,6 +883,12 @@ static void __init aurora_enable_no_outer(void __iomem *base, u32 aux,
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l2c_enable(base, aux, num_lock);
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}
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static void __init aurora_fixup(void __iomem *base, u32 cache_id,
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struct outer_cache_fns *fns)
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{
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sync_reg_offset = AURORA_SYNC_REG;
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}
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static void __init aurora_of_parse(const struct device_node *np,
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u32 *aux_val, u32 *aux_mask)
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{
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@ -828,6 +915,7 @@ static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
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.num_lock = 4,
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.of_parse = aurora_of_parse,
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.enable = l2c_enable,
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.fixup = aurora_fixup,
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.save = aurora_save,
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.outer_cache = {
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.inv_range = aurora_inv_range,
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@ -844,6 +932,7 @@ static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
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.num_lock = 4,
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.of_parse = aurora_of_parse,
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.enable = aurora_enable_no_outer,
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.fixup = aurora_fixup,
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.save = aurora_save,
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.outer_cache = {
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.resume = aurora_resume,
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@ -995,6 +1084,7 @@ static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
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.num_lock = 8,
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.of_parse = pl310_of_parse,
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.enable = l2c_enable,
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.fixup = l2c310_fixup,
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.save = pl310_save,
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.outer_cache = {
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.inv_range = bcm_inv_range,
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