forked from Minki/linux
sata_fsl,mv,nv: prepare for NCQ command completion update
Make the following changes to prepare for NCQ command completion update. Changes made by this patch don't cause any functional difference. * sata_fsl_host_intr(): rename the local variable qc_active to done_mask as that's what it is. * mv_process_crpb_response(): restructure if clause for easier update. * nv_adma_interrupt(): drop unnecessary error variable. * nv_swncq_sdbfis(): drop unnecessary nr_done and return 0 on success. Typo fix. * nv_swncq_dmafis(): drop unused return value and return void. * nv_swncq_host_interrupt(): drop unnecessary return value handling. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Ashish Kalra <ashish.kalra@freescale.com> Cc: Saeed Bishara <saeed@marvell.com> Cc: Mark Lord <liml@rtr.ca> Cc: Robert Hancock <hancockr@shaw.ca> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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af4d6e257d
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752e386c24
@ -1096,7 +1096,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
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{
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struct sata_fsl_host_priv *host_priv = ap->host->private_data;
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void __iomem *hcr_base = host_priv->hcr_base;
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u32 hstatus, qc_active = 0;
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u32 hstatus, done_mask = 0;
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struct ata_queued_cmd *qc;
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u32 SError;
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@ -1116,28 +1116,28 @@ static void sata_fsl_host_intr(struct ata_port *ap)
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}
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/* Read command completed register */
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qc_active = ioread32(hcr_base + CC);
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done_mask = ioread32(hcr_base + CC);
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VPRINTK("Status of all queues :\n");
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VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
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qc_active,
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VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
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done_mask,
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ioread32(hcr_base + CA),
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ioread32(hcr_base + CE),
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ioread32(hcr_base + CQ),
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ap->qc_active);
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if (qc_active & ap->qc_active) {
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if (done_mask & ap->qc_active) {
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int i;
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/* clear CC bit, this will also complete the interrupt */
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iowrite32(qc_active, hcr_base + CC);
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iowrite32(done_mask, hcr_base + CC);
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DPRINTK("Status of all queues :\n");
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DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
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qc_active, ioread32(hcr_base + CA),
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DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
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done_mask, ioread32(hcr_base + CA),
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ioread32(hcr_base + CE));
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for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
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if (qc_active & (1 << i)) {
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if (done_mask & (1 << i)) {
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qc = ata_qc_from_tag(ap, i);
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if (qc) {
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ata_qc_complete(qc);
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@ -1164,7 +1164,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
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/* Spurious Interrupt!! */
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DPRINTK("spurious interrupt!!, CC = 0x%x\n",
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ioread32(hcr_base + CC));
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iowrite32(qc_active, hcr_base + CC);
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iowrite32(done_mask, hcr_base + CC);
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return;
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}
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}
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@ -2716,34 +2716,35 @@ static void mv_err_intr(struct ata_port *ap)
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static void mv_process_crpb_response(struct ata_port *ap,
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struct mv_crpb *response, unsigned int tag, int ncq_enabled)
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{
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u8 ata_status;
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u16 edma_status = le16_to_cpu(response->flags);
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
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if (qc) {
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u8 ata_status;
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u16 edma_status = le16_to_cpu(response->flags);
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/*
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* edma_status from a response queue entry:
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* LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
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* MSB is saved ATA status from command completion.
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*/
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if (!ncq_enabled) {
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u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
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if (err_cause) {
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/*
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* Error will be seen/handled by mv_err_intr().
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* So do nothing at all here.
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*/
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return;
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}
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}
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ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
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if (!ac_err_mask(ata_status))
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ata_qc_complete(qc);
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/* else: leave it for mv_err_intr() */
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} else {
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if (unlikely(!qc)) {
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ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
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__func__, tag);
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return;
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}
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/*
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* edma_status from a response queue entry:
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* LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
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* MSB is saved ATA status from command completion.
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*/
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if (!ncq_enabled) {
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u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
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if (err_cause) {
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/*
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* Error will be seen/handled by
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* mv_err_intr(). So do nothing at all here.
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*/
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return;
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}
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}
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ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
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if (!ac_err_mask(ata_status))
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ata_qc_complete(qc);
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/* else: leave it for mv_err_intr() */
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}
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static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
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@ -1018,7 +1018,7 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
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NV_ADMA_STAT_CPBERR |
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NV_ADMA_STAT_CMD_COMPLETE)) {
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u32 check_commands = notifier_clears[i];
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int pos, error = 0;
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int pos, rc;
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if (status & NV_ADMA_STAT_CPBERR) {
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/* check all active commands */
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@ -1030,10 +1030,12 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
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}
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/* check CPBs for completed commands */
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while ((pos = ffs(check_commands)) && !error) {
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while ((pos = ffs(check_commands))) {
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pos--;
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error = nv_adma_check_cpb(ap, pos,
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rc = nv_adma_check_cpb(ap, pos,
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notifier_error & (1 << pos));
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if (unlikely(rc))
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check_commands = 0;
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check_commands &= ~(1 << pos);
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}
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}
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@ -2129,7 +2131,6 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
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struct nv_swncq_port_priv *pp = ap->private_data;
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struct ata_eh_info *ehi = &ap->link.eh_info;
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u32 sactive;
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int nr_done = 0;
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u32 done_mask;
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int i;
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u8 host_stat;
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@ -2170,22 +2171,21 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
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pp->dhfis_bits &= ~(1 << i);
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pp->dmafis_bits &= ~(1 << i);
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pp->sdbfis_bits |= (1 << i);
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nr_done++;
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}
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}
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if (!ap->qc_active) {
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DPRINTK("over\n");
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nv_swncq_pp_reinit(ap);
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return nr_done;
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return 0;
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}
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if (pp->qc_active & pp->dhfis_bits)
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return nr_done;
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return 0;
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if ((pp->ncq_flags & ncq_saw_backout) ||
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(pp->qc_active ^ pp->dhfis_bits))
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/* if the controller cann't get a device to host register FIS,
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/* if the controller can't get a device to host register FIS,
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* The driver needs to reissue the new command.
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*/
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lack_dhfis = 1;
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@ -2202,7 +2202,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
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if (lack_dhfis) {
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qc = ata_qc_from_tag(ap, pp->last_issue_tag);
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nv_swncq_issue_atacmd(ap, qc);
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return nr_done;
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return 0;
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}
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if (pp->defer_queue.defer_bits) {
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@ -2212,7 +2212,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
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nv_swncq_issue_atacmd(ap, qc);
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}
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return nr_done;
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return 0;
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}
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static inline u32 nv_swncq_tag(struct ata_port *ap)
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@ -2224,7 +2224,7 @@ static inline u32 nv_swncq_tag(struct ata_port *ap)
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return (tag & 0x1f);
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}
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static int nv_swncq_dmafis(struct ata_port *ap)
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static void nv_swncq_dmafis(struct ata_port *ap)
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{
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struct ata_queued_cmd *qc;
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unsigned int rw;
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@ -2239,7 +2239,7 @@ static int nv_swncq_dmafis(struct ata_port *ap)
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qc = ata_qc_from_tag(ap, tag);
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if (unlikely(!qc))
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return 0;
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return;
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rw = qc->tf.flags & ATA_TFLAG_WRITE;
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@ -2254,8 +2254,6 @@ static int nv_swncq_dmafis(struct ata_port *ap)
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dmactl |= ATA_DMA_WR;
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iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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return 1;
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}
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static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
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@ -2265,7 +2263,6 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
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struct ata_eh_info *ehi = &ap->link.eh_info;
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u32 serror;
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u8 ata_stat;
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int rc = 0;
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ata_stat = ap->ops->sff_check_status(ap);
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nv_swncq_irq_clear(ap, fis);
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@ -2310,8 +2307,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
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"dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
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ap->print_id, pp->qc_active, pp->dhfis_bits,
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pp->dmafis_bits, readl(pp->sactive_block));
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rc = nv_swncq_sdbfis(ap);
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if (rc < 0)
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if (nv_swncq_sdbfis(ap) < 0)
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goto irq_error;
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}
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@ -2348,7 +2344,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
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*/
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pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
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pp->ncq_flags |= ncq_saw_dmas;
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rc = nv_swncq_dmafis(ap);
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nv_swncq_dmafis(ap);
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}
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irq_exit:
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