forked from Minki/linux
soundwire: qcom: add runtime pm support
Add support to runtime PM using SoundWire clock stop Mode0 on supported controller instances and soft reset on instances that do not support clock stop. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220228172528.3489-2-srinivas.kandagatla@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
parent
63fadaa2c7
commit
74e79da9fd
@ -11,6 +11,7 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_irq.h>
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#include <linux/of_device.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/slimbus.h>
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#include <linux/slimbus.h>
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@ -20,6 +21,9 @@
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#include <sound/soc.h>
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#include <sound/soc.h>
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#include "bus.h"
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#include "bus.h"
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#define SWRM_COMP_SW_RESET 0x008
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#define SWRM_COMP_STATUS 0x014
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#define SWRM_FRM_GEN_ENABLED BIT(0)
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#define SWRM_COMP_HW_VERSION 0x00
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#define SWRM_COMP_HW_VERSION 0x00
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#define SWRM_COMP_CFG_ADDR 0x04
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#define SWRM_COMP_CFG_ADDR 0x04
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#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
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#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
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@ -29,6 +33,7 @@
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#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
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#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
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#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
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#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
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#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
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#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
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#define SWRM_COMP_MASTER_ID 0x104
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#define SWRM_INTERRUPT_STATUS 0x200
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#define SWRM_INTERRUPT_STATUS 0x200
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#define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
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#define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
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#define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
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#define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
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@ -111,6 +116,13 @@
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#define SWR_MAX_CMD_ID 14
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#define SWR_MAX_CMD_ID 14
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#define MAX_FIFO_RD_RETRY 3
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#define MAX_FIFO_RD_RETRY 3
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#define SWR_OVERFLOW_RETRY_COUNT 30
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#define SWR_OVERFLOW_RETRY_COUNT 30
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#define SWRM_LINK_STATUS_RETRY_CNT 100
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enum {
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MASTER_ID_WSA = 1,
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MASTER_ID_RX,
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MASTER_ID_TX
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};
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struct qcom_swrm_port_config {
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struct qcom_swrm_port_config {
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u8 si;
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u8 si;
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@ -159,6 +171,7 @@ struct qcom_swrm_ctrl {
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u32 slave_status;
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u32 slave_status;
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u32 wr_fifo_depth;
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u32 wr_fifo_depth;
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u32 rd_fifo_depth;
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u32 rd_fifo_depth;
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bool clock_stop_not_supported;
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};
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};
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struct qcom_swrm_data {
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struct qcom_swrm_data {
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@ -497,6 +510,7 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
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u32 i;
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u32 i;
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int devnum;
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int devnum;
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int ret = IRQ_HANDLED;
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int ret = IRQ_HANDLED;
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clk_prepare_enable(swrm->hclk);
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swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
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swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
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intr_sts_masked = intr_sts & swrm->intr_mask;
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intr_sts_masked = intr_sts & swrm->intr_mask;
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@ -604,6 +618,7 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
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intr_sts_masked = intr_sts & swrm->intr_mask;
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intr_sts_masked = intr_sts & swrm->intr_mask;
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} while (intr_sts_masked);
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} while (intr_sts_masked);
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clk_disable_unprepare(swrm->hclk);
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return ret;
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return ret;
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}
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}
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@ -1017,6 +1032,15 @@ static int qcom_swrm_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *codec_dai;
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struct snd_soc_dai *codec_dai;
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int ret, i;
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int ret, i;
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ret = pm_runtime_get_sync(ctrl->dev);
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if (ret < 0 && ret != -EACCES) {
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dev_err_ratelimited(ctrl->dev,
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"pm_runtime_get_sync failed in %s, ret %d\n",
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__func__, ret);
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pm_runtime_put_noidle(ctrl->dev);
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return ret;
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}
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sruntime = sdw_alloc_stream(dai->name);
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sruntime = sdw_alloc_stream(dai->name);
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if (!sruntime)
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if (!sruntime)
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return -ENOMEM;
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return -ENOMEM;
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@ -1044,6 +1068,9 @@ static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
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sdw_release_stream(ctrl->sruntime[dai->id]);
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sdw_release_stream(ctrl->sruntime[dai->id]);
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ctrl->sruntime[dai->id] = NULL;
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ctrl->sruntime[dai->id] = NULL;
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pm_runtime_mark_last_busy(ctrl->dev);
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pm_runtime_put_autosuspend(ctrl->dev);
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}
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}
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static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
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static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
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@ -1197,12 +1224,23 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
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static int swrm_reg_show(struct seq_file *s_file, void *data)
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static int swrm_reg_show(struct seq_file *s_file, void *data)
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{
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{
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struct qcom_swrm_ctrl *swrm = s_file->private;
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struct qcom_swrm_ctrl *swrm = s_file->private;
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int reg, reg_val;
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int reg, reg_val, ret;
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ret = pm_runtime_get_sync(swrm->dev);
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if (ret < 0 && ret != -EACCES) {
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dev_err_ratelimited(swrm->dev,
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"pm_runtime_get_sync failed in %s, ret %d\n",
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__func__, ret);
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pm_runtime_put_noidle(swrm->dev);
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}
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for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
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for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
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swrm->reg_read(swrm, reg, ®_val);
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swrm->reg_read(swrm, reg, ®_val);
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seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
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seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
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}
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}
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pm_runtime_mark_last_busy(swrm->dev);
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pm_runtime_put_autosuspend(swrm->dev);
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return 0;
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return 0;
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}
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}
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@ -1267,6 +1305,7 @@ static int qcom_swrm_probe(struct platform_device *pdev)
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ctrl->bus.ops = &qcom_swrm_ops;
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ctrl->bus.ops = &qcom_swrm_ops;
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ctrl->bus.port_ops = &qcom_swrm_port_ops;
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ctrl->bus.port_ops = &qcom_swrm_port_ops;
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ctrl->bus.compute_params = &qcom_swrm_compute_params;
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ctrl->bus.compute_params = &qcom_swrm_compute_params;
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ctrl->bus.clk_stop_timeout = 300;
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ret = qcom_swrm_get_port_config(ctrl);
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ret = qcom_swrm_get_port_config(ctrl);
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if (ret)
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if (ret)
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@ -1319,6 +1358,21 @@ static int qcom_swrm_probe(struct platform_device *pdev)
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(ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
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(ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
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ctrl->version & 0xffff);
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ctrl->version & 0xffff);
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pm_runtime_set_autosuspend_delay(dev, 3000);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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/* Clk stop is not supported on WSA Soundwire masters */
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if (ctrl->version <= 0x01030000) {
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ctrl->clock_stop_not_supported = true;
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} else {
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ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
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if (val == MASTER_ID_WSA)
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ctrl->clock_stop_not_supported = true;
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}
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
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ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
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debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
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debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
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@ -1345,6 +1399,105 @@ static int qcom_swrm_remove(struct platform_device *pdev)
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return 0;
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return 0;
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}
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}
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static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
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{
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int retry = SWRM_LINK_STATUS_RETRY_CNT;
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int comp_sts;
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do {
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swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
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if (comp_sts & SWRM_FRM_GEN_ENABLED)
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return true;
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usleep_range(500, 510);
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} while (retry--);
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dev_err(swrm->dev, "%s: link status not %s\n", __func__,
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comp_sts && SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
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return false;
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}
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static int swrm_runtime_resume(struct device *dev)
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{
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struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
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int ret;
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clk_prepare_enable(ctrl->hclk);
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if (ctrl->clock_stop_not_supported) {
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reinit_completion(&ctrl->enumeration);
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ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
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usleep_range(100, 105);
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qcom_swrm_init(ctrl);
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usleep_range(100, 105);
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if (!swrm_wait_for_frame_gen_enabled(ctrl))
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dev_err(ctrl->dev, "link failed to connect\n");
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/* wait for hw enumeration to complete */
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wait_for_completion_timeout(&ctrl->enumeration,
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msecs_to_jiffies(TIMEOUT_MS));
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qcom_swrm_get_device_status(ctrl);
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sdw_handle_slave_status(&ctrl->bus, ctrl->status);
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} else {
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ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
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ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
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SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
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ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
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ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
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ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
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usleep_range(100, 105);
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if (!swrm_wait_for_frame_gen_enabled(ctrl))
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dev_err(ctrl->dev, "link failed to connect\n");
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ret = sdw_bus_exit_clk_stop(&ctrl->bus);
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if (ret < 0)
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dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
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}
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return 0;
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}
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static int __maybe_unused swrm_runtime_suspend(struct device *dev)
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{
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struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
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int ret;
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if (!ctrl->clock_stop_not_supported) {
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/* Mask bus clash interrupt */
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ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
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ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
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ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
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/* Prepare slaves for clock stop */
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ret = sdw_bus_prep_clk_stop(&ctrl->bus);
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if (ret < 0 && ret != -ENODATA) {
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dev_err(dev, "prepare clock stop failed %d", ret);
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return ret;
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}
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ret = sdw_bus_clk_stop(&ctrl->bus);
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if (ret < 0 && ret != -ENODATA) {
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dev_err(dev, "bus clock stop failed %d", ret);
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return ret;
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}
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}
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clk_disable_unprepare(ctrl->hclk);
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usleep_range(300, 305);
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return 0;
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}
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static const struct dev_pm_ops swrm_dev_pm_ops = {
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SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
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};
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static const struct of_device_id qcom_swrm_of_match[] = {
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static const struct of_device_id qcom_swrm_of_match[] = {
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{ .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
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{ .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
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{ .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
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{ .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
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@ -1359,6 +1512,7 @@ static struct platform_driver qcom_swrm_driver = {
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.driver = {
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.driver = {
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.name = "qcom-soundwire",
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.name = "qcom-soundwire",
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.of_match_table = qcom_swrm_of_match,
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.of_match_table = qcom_swrm_of_match,
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.pm = &swrm_dev_pm_ops,
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}
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}
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};
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};
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module_platform_driver(qcom_swrm_driver);
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module_platform_driver(qcom_swrm_driver);
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