dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding compatible strings to enable support for TI AM654x/J721E SoCs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -40,6 +40,7 @@ Required properties:
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"ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
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"ti,am43xx-phy-gmii-sel" for am43xx platform
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"ti,dm814-phy-gmii-sel" for dm814x platform
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"ti,am654-phy-gmii-sel" for AM654x/J721E platform
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- reg : Address and length of the register set for the device
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- #phy-cells : must be 2.
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cell 1 - CPSW port number (starting from 1)
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