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powerpc: Only do ERAT invalidate on radix context switch on P9 DD1

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From: Michael Neuling <mikey@neuling.org>

On P9 (Nimbus) DD2 and later, in radix mode, the move to the PID
register will implicitly invalidate the user space ERAT entries
and leave the kernel ones alone. Thus the only thing needed is
an isync() to synchronize this with subsequent uaccess's

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Benjamin Herrenschmidt 2017-06-25 15:08:46 -05:00 committed by Michael Ellerman
parent 8e3f1b1d82
commit 74e27c6af5
1 changed files with 10 additions and 5 deletions
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15
arch/powerpc/mm/mmu_context_book3s64.c
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@ -235,10 +235,15 @@ void destroy_context(struct mm_struct *mm)
#ifdef CONFIG_PPC_RADIX_MMU #ifdef CONFIG_PPC_RADIX_MMU
void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next) void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
{ {
asm volatile("isync": : :"memory");
mtspr(SPRN_PID, next->context.id); if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
asm volatile("isync \n" isync();
PPC_SLBIA(0x7) mtspr(SPRN_PID, next->context.id);
: : :"memory"); isync();
asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
} else {
mtspr(SPRN_PID, next->context.id);
isync();
}
} }
#endif #endif