forked from Minki/linux
drivers/video/i810/i810-i2c.c: fix i2c bus handling
These patch fix a longstanding bug in the i810 frame buffer driver. The handling of the i2c bus is wrong: A 1 bit should not written to the i2c, these will be done by switch the i2c to input. Driving an 1 bit active is against the i2c spec. An active driven of a 1 bit will result in very strange error, depending which side is the more powerful one. In my case it depends on the temperature of the Display-Controller-EEprom: With an cold eprom a got the correct EDID datas, with a warm one some of the 1 bits was 0 :-( The same bug is also in the intelfb driver in the file drivers/video/intelfb/intelfb_i2c.c. The functions intelfb_gpio_setscl() and intelfb_gpio_setsda() do drive the 1 bit active to the i2c bus. But since i have no card which is used by the intelfb driver i cannot fix it. Signed-off-by: Stefani Seibold <stefani@seibold.net> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Jean Delvare <khali@linux-fr.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -45,8 +45,10 @@ static void i810i2c_setscl(void *data, int state)
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struct i810fb_par *par = chan->par;
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struct i810fb_par *par = chan->par;
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u8 __iomem *mmio = par->mmio_start_virtual;
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u8 __iomem *mmio = par->mmio_start_virtual;
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i810_writel(mmio, chan->ddc_base, (state ? SCL_VAL_OUT : 0) | SCL_DIR |
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if (state)
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SCL_DIR_MASK | SCL_VAL_MASK);
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i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK);
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else
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i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
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i810_readl(mmio, chan->ddc_base); /* flush posted write */
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i810_readl(mmio, chan->ddc_base); /* flush posted write */
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}
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}
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@ -56,8 +58,10 @@ static void i810i2c_setsda(void *data, int state)
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struct i810fb_par *par = chan->par;
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struct i810fb_par *par = chan->par;
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u8 __iomem *mmio = par->mmio_start_virtual;
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u8 __iomem *mmio = par->mmio_start_virtual;
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i810_writel(mmio, chan->ddc_base, (state ? SDA_VAL_OUT : 0) | SDA_DIR |
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if (state)
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SDA_DIR_MASK | SDA_VAL_MASK);
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i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK);
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else
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i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
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i810_readl(mmio, chan->ddc_base); /* flush posted write */
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i810_readl(mmio, chan->ddc_base); /* flush posted write */
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}
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}
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