forked from Minki/linux
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu from Greg Ungerer: "This contains five fixes. Four fix build problems introduced by recent clean up and merging of the m68k timer and ptrace code. The other fixes the 528x ColdFire CPU QSPI base address definition, missed in the ColdFire QSPI cleanup." * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68k: make syscall_trace_enter/leave exist for non-MMU classic m68k types m68knommu: fix 68360 local setting of timer interrupt handler m68knommu: fix 68328 local setting of timer interrupt handler m68k: fix inclusion of arch_gettimeoffset for non-MMU 68k classic CPU types m68knommu: m528x qspi definition fix
This commit is contained in:
commit
7452ca511c
@ -86,7 +86,7 @@
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/*
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/*
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* QSPI module.
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* QSPI module.
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*/
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*/
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#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
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#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
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#define MCFQSPI_SIZE 0x40
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#define MCFQSPI_SIZE 0x40
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#define MCFQSPI_CS0 147
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#define MCFQSPI_CS0 147
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@ -286,7 +286,7 @@ asmlinkage void syscall_trace(void)
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}
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}
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}
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}
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#ifdef CONFIG_COLDFIRE
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#if defined(CONFIG_COLDFIRE) || !defined(CONFIG_MMU)
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asmlinkage int syscall_trace_enter(void)
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asmlinkage int syscall_trace_enter(void)
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{
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{
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int ret = 0;
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int ret = 0;
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@ -85,7 +85,7 @@ void __init time_init(void)
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mach_sched_init(timer_interrupt);
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mach_sched_init(timer_interrupt);
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}
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}
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#ifdef CONFIG_M68KCLASSIC
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#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
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u32 arch_gettimeoffset(void)
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u32 arch_gettimeoffset(void)
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{
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{
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@ -108,4 +108,4 @@ static int __init rtc_init(void)
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module_init(rtc_init);
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module_init(rtc_init);
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#endif /* CONFIG_M68KCLASSIC */
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#endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */
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@ -53,6 +53,7 @@
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#endif
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#endif
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static u32 m68328_tick_cnt;
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static u32 m68328_tick_cnt;
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static irq_handler_t timer_interrupt;
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/***************************************************************************/
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/***************************************************************************/
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@ -62,7 +63,7 @@ static irqreturn_t hw_tick(int irq, void *dummy)
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TSTAT &= 0;
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TSTAT &= 0;
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m68328_tick_cnt += TICKS_PER_JIFFY;
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m68328_tick_cnt += TICKS_PER_JIFFY;
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return arch_timer_interrupt(irq, dummy);
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return timer_interrupt(irq, dummy);
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}
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}
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/***************************************************************************/
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/***************************************************************************/
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@ -99,7 +100,7 @@ static struct clocksource m68328_clk = {
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/***************************************************************************/
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/***************************************************************************/
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void hw_timer_init(void)
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void hw_timer_init(irq_handler_t handler)
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{
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{
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/* disable timer 1 */
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/* disable timer 1 */
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TCTL = 0;
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TCTL = 0;
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@ -115,6 +116,7 @@ void hw_timer_init(void)
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/* Enable timer 1 */
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/* Enable timer 1 */
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TCTL |= TCTL_TEN;
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TCTL |= TCTL_TEN;
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clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
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clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
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timer_interrupt = handler;
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}
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}
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/***************************************************************************/
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/***************************************************************************/
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@ -35,6 +35,7 @@ extern void m360_cpm_reset(void);
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#define OSCILLATOR (unsigned long int)33000000
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#define OSCILLATOR (unsigned long int)33000000
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#endif
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#endif
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static irq_handler_t timer_interrupt;
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unsigned long int system_clock;
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unsigned long int system_clock;
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extern QUICC *pquicc;
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extern QUICC *pquicc;
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@ -52,7 +53,7 @@ static irqreturn_t hw_tick(int irq, void *dummy)
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pquicc->timer_ter1 = 0x0002; /* clear timer event */
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pquicc->timer_ter1 = 0x0002; /* clear timer event */
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return arch_timer_interrupt(irq, dummy);
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return timer_interrupt(irq, dummy);
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}
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}
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static struct irqaction m68360_timer_irq = {
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static struct irqaction m68360_timer_irq = {
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@ -61,7 +62,7 @@ static struct irqaction m68360_timer_irq = {
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.handler = hw_tick,
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.handler = hw_tick,
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};
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};
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void hw_timer_init(void)
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void hw_timer_init(irq_handler_t handler)
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{
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{
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unsigned char prescaler;
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unsigned char prescaler;
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unsigned short tgcr_save;
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unsigned short tgcr_save;
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@ -94,6 +95,8 @@ void hw_timer_init(void)
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pquicc->timer_ter1 = 0x0003; /* clear timer events */
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pquicc->timer_ter1 = 0x0003; /* clear timer events */
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timer_interrupt = handler;
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/* enable timer 1 interrupt in CIMR */
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/* enable timer 1 interrupt in CIMR */
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setup_irq(CPMVEC_TIMER1, &m68360_timer_irq);
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setup_irq(CPMVEC_TIMER1, &m68360_timer_irq);
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