forked from Minki/linux
net/mlx5e: Add PCIe outbound stalls counters
outbound_pci_stalled_rd - The percentage of time within the last second that the NIC had outbound non-posted read requests but could not perform the operation due to insufficient non-posted credits. outbound_pci_stalled_wr - The percentage of time within the last second that the NIC had outbound posted writes requests but could not perform the operation due to insufficient posted credits. outbound_pci_stalled_rd_events - The number of events where outbound_pci_stalled_rd was above the threshold. outbound_pci_stalled_wr_events - The number of events where outbound_pci_stalled_wr was above the threshold. Signed-off-by: Gal Pressman <galp@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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5405fa26c2
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@ -246,6 +246,10 @@ static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
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strcpy(data + (idx++) * ETH_GSTRING_LEN,
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pcie_perf_stats_desc[i].format);
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for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
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strcpy(data + (idx++) * ETH_GSTRING_LEN,
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pcie_perf_stall_stats_desc[i].format);
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for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
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for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
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sprintf(data + (idx++) * ETH_GSTRING_LEN,
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@ -377,6 +381,10 @@ void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
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data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
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pcie_perf_stats_desc, i);
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for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
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data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
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pcie_perf_stall_stats_desc, i);
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for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
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for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
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data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
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@ -305,6 +305,13 @@ static const struct counter_desc pcie_perf_stats_desc[] = {
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{ "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
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};
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static const struct counter_desc pcie_perf_stall_stats_desc[] = {
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{ "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
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{ "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
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{ "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
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{ "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
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};
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struct mlx5e_rq_stats {
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u64 packets;
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u64 bytes;
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@ -397,6 +404,9 @@ static const struct counter_desc sq_stats_desc[] = {
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#define NUM_PCIE_PERF_COUNTERS(priv) \
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(ARRAY_SIZE(pcie_perf_stats_desc) * \
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MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
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#define NUM_PCIE_PERF_STALL_COUNTERS(priv) \
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(ARRAY_SIZE(pcie_perf_stall_stats_desc) * \
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MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
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#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \
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ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
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#define NUM_PPORT_PER_PRIO_PFC_COUNTERS \
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@ -407,7 +417,8 @@ static const struct counter_desc sq_stats_desc[] = {
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NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv) + \
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NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \
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NUM_PPORT_PRIO)
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#define NUM_PCIE_COUNTERS(priv) NUM_PCIE_PERF_COUNTERS(priv)
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#define NUM_PCIE_COUNTERS(priv) (NUM_PCIE_PERF_COUNTERS(priv) + \
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NUM_PCIE_PERF_STALL_COUNTERS(priv))
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#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
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#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
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