media: i2c: Support 19.2MHz input clock in ov8865
The ov8865 driver as written expects a 24MHz input clock, but the sensor is sometimes found on x86 platforms with a 19.2MHz input clock supplied. Add a set of PLL configurations to the driver to support that rate too. As ACPI doesn't auto-configure the clock rate, check for a clock-frequency during probe and set that rate if one is found. Signed-off-by: Daniel Scally <djrscally@gmail.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Daniel Scally
Mauro Carvalho Chehab
parent
ba0c8045ea
commit
73dcffeb2f
@ -21,10 +21,6 @@
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#include <media/v4l2-image-sizes.h>
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#include <media/v4l2-mediabus.h>
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/* Clock rate */
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#define OV8865_EXTCLK_RATE 24000000
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/* Register definitions */
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/* System */
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@ -567,6 +563,25 @@ struct ov8865_sclk_config {
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unsigned int sclk_div;
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};
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struct ov8865_pll_configs {
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const struct ov8865_pll1_config *pll1_config;
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const struct ov8865_pll2_config *pll2_config_native;
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const struct ov8865_pll2_config *pll2_config_binning;
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};
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/* Clock rate */
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enum extclk_rate {
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OV8865_19_2_MHZ,
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OV8865_24_MHZ,
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OV8865_NUM_SUPPORTED_RATES
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};
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static const unsigned long supported_extclk_rates[] = {
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[OV8865_19_2_MHZ] = 19200000,
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[OV8865_24_MHZ] = 24000000,
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};
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/*
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* General formulas for (array-centered) mode calculation:
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* - photo_array_width = 3296
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@ -635,9 +650,7 @@ struct ov8865_mode {
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struct v4l2_fract frame_interval;
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const struct ov8865_pll1_config *pll1_config;
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const struct ov8865_pll2_config *pll2_config;
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const struct ov8865_sclk_config *sclk_config;
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bool pll2_binning;
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const struct ov8865_register_value *register_values;
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unsigned int register_values_count;
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@ -665,6 +678,9 @@ struct ov8865_sensor {
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struct regulator *avdd;
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struct regulator *dvdd;
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struct regulator *dovdd;
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unsigned long extclk_rate;
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const struct ov8865_pll_configs *pll_configs;
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struct clk *extclk;
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struct v4l2_fwnode_endpoint endpoint;
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@ -680,43 +696,70 @@ struct ov8865_sensor {
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/* Static definitions */
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/*
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* EXTCLK = 24 MHz
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* PHY_SCLK = 720 MHz
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* MIPI_PCLK = 90 MHz
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*/
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static const struct ov8865_pll1_config ov8865_pll1_config_native = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 0,
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.pll_mul = 30,
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.m_div = 1,
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.mipi_div = 3,
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.pclk_div = 1,
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.sys_pre_div = 1,
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.sys_div = 2,
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static const struct ov8865_pll1_config ov8865_pll1_config_native_19_2mhz = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 2,
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.pll_mul = 75,
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.m_div = 1,
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.mipi_div = 3,
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.pclk_div = 1,
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.sys_pre_div = 1,
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.sys_div = 2,
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};
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static const struct ov8865_pll1_config ov8865_pll1_config_native_24mhz = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 0,
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.pll_mul = 30,
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.m_div = 1,
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.mipi_div = 3,
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.pclk_div = 1,
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.sys_pre_div = 1,
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.sys_div = 2,
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};
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/*
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* EXTCLK = 24 MHz
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* DAC_CLK = 360 MHz
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* SCLK = 144 MHz
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*/
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static const struct ov8865_pll2_config ov8865_pll2_config_native = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 0,
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.pll_mul = 30,
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.dac_div = 2,
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.sys_pre_div = 5,
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.sys_div = 0,
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static const struct ov8865_pll2_config ov8865_pll2_config_native_19_2mhz = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 5,
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.pll_mul = 75,
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.dac_div = 1,
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.sys_pre_div = 1,
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.sys_div = 3,
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};
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static const struct ov8865_pll2_config ov8865_pll2_config_native_24mhz = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 0,
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.pll_mul = 30,
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.dac_div = 2,
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.sys_pre_div = 5,
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.sys_div = 0,
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};
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/*
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* EXTCLK = 24 MHz
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* DAC_CLK = 360 MHz
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* SCLK = 72 MHz
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*/
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static const struct ov8865_pll2_config ov8865_pll2_config_binning = {
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static const struct ov8865_pll2_config ov8865_pll2_config_binning_19_2mhz = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 2,
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.pll_mul = 75,
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.dac_div = 2,
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.sys_pre_div = 10,
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.sys_div = 0,
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};
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static const struct ov8865_pll2_config ov8865_pll2_config_binning_24mhz = {
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.pll_pre_div_half = 1,
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.pll_pre_div = 0,
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.pll_mul = 30,
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@ -725,6 +768,23 @@ static const struct ov8865_pll2_config ov8865_pll2_config_binning = {
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.sys_div = 0,
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};
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static const struct ov8865_pll_configs ov8865_pll_configs_19_2mhz = {
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.pll1_config = &ov8865_pll1_config_native_19_2mhz,
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.pll2_config_native = &ov8865_pll2_config_native_19_2mhz,
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.pll2_config_binning = &ov8865_pll2_config_binning_19_2mhz,
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};
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static const struct ov8865_pll_configs ov8865_pll_configs_24mhz = {
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.pll1_config = &ov8865_pll1_config_native_24mhz,
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.pll2_config_native = &ov8865_pll2_config_native_24mhz,
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.pll2_config_binning = &ov8865_pll2_config_binning_24mhz,
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};
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static const struct ov8865_pll_configs *ov8865_pll_configs[] = {
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&ov8865_pll_configs_19_2mhz,
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&ov8865_pll_configs_24mhz,
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};
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static const struct ov8865_sclk_config ov8865_sclk_config_native = {
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.sys_sel = 1,
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.sclk_sel = 0,
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@ -934,9 +994,7 @@ static const struct ov8865_mode ov8865_modes[] = {
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.frame_interval = { 1, 30 },
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/* PLL */
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.pll1_config = &ov8865_pll1_config_native,
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.pll2_config = &ov8865_pll2_config_native,
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.sclk_config = &ov8865_sclk_config_native,
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.pll2_binning = false,
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/* Registers */
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.register_values = ov8865_register_values_native,
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@ -990,9 +1048,7 @@ static const struct ov8865_mode ov8865_modes[] = {
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.frame_interval = { 1, 30 },
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/* PLL */
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.pll1_config = &ov8865_pll1_config_native,
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.pll2_config = &ov8865_pll2_config_native,
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.sclk_config = &ov8865_sclk_config_native,
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.pll2_binning = false,
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/* Registers */
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.register_values = ov8865_register_values_native,
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@ -1050,9 +1106,7 @@ static const struct ov8865_mode ov8865_modes[] = {
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.frame_interval = { 1, 30 },
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/* PLL */
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.pll1_config = &ov8865_pll1_config_native,
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.pll2_config = &ov8865_pll2_config_binning,
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.sclk_config = &ov8865_sclk_config_native,
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.pll2_binning = true,
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/* Registers */
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.register_values = ov8865_register_values_binning,
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@ -1116,9 +1170,7 @@ static const struct ov8865_mode ov8865_modes[] = {
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.frame_interval = { 1, 90 },
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/* PLL */
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.pll1_config = &ov8865_pll1_config_native,
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.pll2_config = &ov8865_pll2_config_binning,
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.sclk_config = &ov8865_sclk_config_native,
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.pll2_binning = true,
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/* Registers */
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.register_values = ov8865_register_values_binning,
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@ -1513,12 +1565,11 @@ static int ov8865_isp_configure(struct ov8865_sensor *sensor)
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static unsigned long ov8865_mode_pll1_rate(struct ov8865_sensor *sensor,
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const struct ov8865_mode *mode)
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{
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const struct ov8865_pll1_config *config = mode->pll1_config;
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unsigned long extclk_rate;
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const struct ov8865_pll1_config *config;
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unsigned long pll1_rate;
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extclk_rate = clk_get_rate(sensor->extclk);
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pll1_rate = extclk_rate * config->pll_mul / config->pll_pre_div_half;
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config = sensor->pll_configs->pll1_config;
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pll1_rate = sensor->extclk_rate * config->pll_mul / config->pll_pre_div_half;
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switch (config->pll_pre_div) {
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case 0:
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@ -1552,10 +1603,12 @@ static int ov8865_mode_pll1_configure(struct ov8865_sensor *sensor,
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const struct ov8865_mode *mode,
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u32 mbus_code)
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{
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const struct ov8865_pll1_config *config = mode->pll1_config;
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const struct ov8865_pll1_config *config;
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u8 value;
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int ret;
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config = sensor->pll_configs->pll1_config;
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switch (mbus_code) {
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case MEDIA_BUS_FMT_SBGGR10_1X10:
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value = OV8865_MIPI_BIT_SEL(10);
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@ -1622,9 +1675,12 @@ static int ov8865_mode_pll1_configure(struct ov8865_sensor *sensor,
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static int ov8865_mode_pll2_configure(struct ov8865_sensor *sensor,
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const struct ov8865_mode *mode)
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{
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const struct ov8865_pll2_config *config = mode->pll2_config;
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const struct ov8865_pll2_config *config;
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int ret;
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config = mode->pll2_binning ? sensor->pll_configs->pll2_config_binning :
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sensor->pll_configs->pll2_config_native;
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ret = ov8865_write(sensor, OV8865_PLL_CTRL12_REG,
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OV8865_PLL_CTRL12_PRE_DIV_HALF(config->pll_pre_div_half) |
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OV8865_PLL_CTRL12_DAC_DIV(config->dac_div));
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@ -1658,7 +1714,7 @@ static int ov8865_mode_pll2_configure(struct ov8865_sensor *sensor,
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static int ov8865_mode_sclk_configure(struct ov8865_sensor *sensor,
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const struct ov8865_mode *mode)
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{
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const struct ov8865_sclk_config *config = mode->sclk_config;
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const struct ov8865_sclk_config *config = &ov8865_sclk_config_native;
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int ret;
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ret = ov8865_write(sensor, OV8865_CLK_SEL0_REG,
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@ -2053,9 +2109,11 @@ static int ov8865_mode_configure(struct ov8865_sensor *sensor,
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static unsigned long ov8865_mode_mipi_clk_rate(struct ov8865_sensor *sensor,
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const struct ov8865_mode *mode)
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{
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const struct ov8865_pll1_config *config = mode->pll1_config;
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const struct ov8865_pll1_config *config;
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unsigned long pll1_rate;
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config = sensor->pll_configs->pll1_config;
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pll1_rate = ov8865_mode_pll1_rate(sensor, mode);
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return pll1_rate / config->m_div / 2;
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@ -2783,7 +2841,8 @@ static int ov8865_probe(struct i2c_client *client)
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struct ov8865_sensor *sensor;
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struct v4l2_subdev *subdev;
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struct media_pad *pad;
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unsigned long rate;
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unsigned int rate = 0;
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unsigned int i;
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int ret;
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sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
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@ -2852,19 +2911,51 @@ static int ov8865_probe(struct i2c_client *client)
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/* External Clock */
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sensor->extclk = devm_clk_get(dev, NULL);
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if (IS_ERR(sensor->extclk)) {
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if (PTR_ERR(sensor->extclk) == -ENOENT) {
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dev_info(dev, "no external clock found, continuing...\n");
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sensor->extclk = NULL;
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} else if (IS_ERR(sensor->extclk)) {
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dev_err(dev, "failed to get external clock\n");
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ret = PTR_ERR(sensor->extclk);
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goto error_endpoint;
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}
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rate = clk_get_rate(sensor->extclk);
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if (rate != OV8865_EXTCLK_RATE) {
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dev_err(dev, "clock rate %lu Hz is unsupported\n", rate);
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/*
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* We could have either a 24MHz or 19.2MHz clock rate from either dt or
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* ACPI...but we also need to support the weird IPU3 case which will
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* have an external clock AND a clock-frequency property. Check for the
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* clock-frequency property and if found, set that rate if we managed
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* to acquire a clock. This should cover the ACPI case. If the system
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* uses devicetree then the configured rate should already be set, so
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* we can just read it.
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*/
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ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
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&rate);
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if (!ret && sensor->extclk) {
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ret = clk_set_rate(sensor->extclk, rate);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to set clock rate\n");
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} else if (ret && !sensor->extclk) {
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return dev_err_probe(dev, ret, "invalid clock config\n");
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}
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sensor->extclk_rate = rate ? rate : clk_get_rate(sensor->extclk);
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for (i = 0; i < ARRAY_SIZE(supported_extclk_rates); i++) {
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if (sensor->extclk_rate == supported_extclk_rates[i])
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break;
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}
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if (i == ARRAY_SIZE(supported_extclk_rates)) {
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dev_err(dev, "clock rate %lu Hz is unsupported\n",
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sensor->extclk_rate);
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ret = -EINVAL;
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goto error_endpoint;
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}
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sensor->pll_configs = ov8865_pll_configs[i];
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/* Subdev, entity and pad */
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subdev = &sensor->subdev;
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