forked from Minki/linux
[MIPS] Routerboard 532: Support for base system
Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
36a0a3cd45
commit
73b4390fb2
@ -558,6 +558,24 @@ config MACH_TX39XX
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config MACH_TX49XX
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bool "Toshiba TX49 series based machines"
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config MIKROTIK_RB532
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bool "Mikrotik RB532 boards"
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select CEVT_R4K
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select CSRC_R4K
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select DMA_NONCOHERENT
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select GENERIC_HARDIRQS_NO__DO_IRQ
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select HW_HAS_PCI
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select IRQ_CPU
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SWAP_IO_SPACE
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select BOOT_RAW
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select GENERIC_GPIO
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help
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Support the Mikrotik(tm) RouterBoard 532 series,
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based on the IDT RC32434 SoC.
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config WR_PPMC
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bool "Wind River PPMC board"
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select CEVT_R4K
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@ -899,7 +917,7 @@ config BOOT_ELF32
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config MIPS_L1_CACHE_SHIFT
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int
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default "4" if MACH_DECSTATION
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default "4" if MACH_DECSTATION || MIKROTIK_RB532
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default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
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default "4" if PMC_MSP4200_EVAL
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default "5"
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@ -559,6 +559,13 @@ load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000
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#
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core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/
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#
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# Routerboard 532 board
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#
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core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/
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cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
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load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
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#
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# Toshiba RBTX4927 board or
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# Toshiba RBTX4937 board
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1314
arch/mips/configs/rb532_defconfig
Normal file
1314
arch/mips/configs/rb532_defconfig
Normal file
File diff suppressed because it is too large
Load Diff
@ -49,3 +49,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
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obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
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obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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69
arch/mips/pci/fixup-rc32434.c
Normal file
69
arch/mips/pci/fixup-rc32434.c
Normal file
@ -0,0 +1,69 @@
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/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* stevel@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/mach-rc32434/rc32434.h>
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static int __devinitdata irq_map[2][12] = {
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{0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
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{0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3}
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};
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int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = 0;
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if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12)
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irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
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return irq + GROUP4_IRQ_BASE + 4;
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}
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static void rc32434_pci_early_fixup(struct pci_dev *dev)
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{
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if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
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/* disable prefetched memory range */
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pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
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pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
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}
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}
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/*
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* The fixup applies to both the IDT and VIA devices present on the board
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*/
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, rc32434_pci_early_fixup);
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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207
arch/mips/pci/ops-rc32434.c
Normal file
207
arch/mips/pci/ops-rc32434.c
Normal file
@ -0,0 +1,207 @@
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/*
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* BRIEF MODULE DESCRIPTION
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* pci_ops for IDT EB434 board
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*
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* Copyright 2004 IDT Inc. (rischelp@idt.com)
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* Copyright 2006 Felix Fietkau <nbd@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/mach-rc32434/rc32434.h>
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#include <asm/mach-rc32434/pci.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#define PCI_CFG_SET(bus, slot, func, off) \
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(rc32434_pci->pcicfga = (0x80000000 | \
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((bus) << 16) | ((slot)<<11) | \
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((func)<<8) | (off)))
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static inline int config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn,
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unsigned char where, u32 *data)
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{
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unsigned int slot = PCI_SLOT(devfn);
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u8 func = PCI_FUNC(devfn);
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/* Setup address */
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PCI_CFG_SET(bus->number, slot, func, where);
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rc32434_sync();
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if (access_type == PCI_ACCESS_WRITE)
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rc32434_pci->pcicfgd = *data;
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else
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*data = rc32434_pci->pcicfgd;
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rc32434_sync();
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return 0;
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}
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/*
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* We can't address 8 and 16 bit words directly. Instead we have to
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* read/write a 32bit word and mask/modify the data we actually want.
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*/
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static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
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int where, u8 *val)
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{
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u32 data;
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int ret;
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
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*val = (data >> ((where & 3) << 3)) & 0xff;
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return ret;
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}
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static int read_config_word(struct pci_bus *bus, unsigned int devfn,
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int where, u16 *val)
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{
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u32 data;
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int ret;
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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return ret;
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}
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static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, u32 *val)
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{
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int ret;
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int delay = 1;
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/*
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* Don't scan too far, else there will be errors with plugged in
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* daughterboard (rb564).
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*/
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if (bus->number == 0 && PCI_SLOT(devfn) > 21)
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return 0;
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retry:
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
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/*
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* Certain devices react delayed at device scan time, this
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* gives them time to settle
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*/
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if (where == PCI_VENDOR_ID) {
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if (ret == 0xffffffff || ret == 0x00000000 ||
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ret == 0x0000ffff || ret == 0xffff0000) {
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if (delay > 4)
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return 0;
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delay *= 2;
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msleep(delay);
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goto retry;
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}
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}
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return ret;
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}
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static int
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write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
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u8 val)
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{
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u32 data = 0;
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return -1;
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
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u16 val)
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{
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u32 data = 0;
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return -1;
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
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u32 val)
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{
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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switch (size) {
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case 1:
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return read_config_byte(bus, devfn, where, (u8 *) val);
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case 2:
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return read_config_word(bus, devfn, where, (u16 *) val);
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default:
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return read_config_dword(bus, devfn, where, val);
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}
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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switch (size) {
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case 1:
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return write_config_byte(bus, devfn, where, (u8) val);
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case 2:
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return write_config_word(bus, devfn, where, (u16) val);
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default:
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return write_config_dword(bus, devfn, where, val);
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}
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}
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struct pci_ops rc32434_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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221
arch/mips/pci/pci-rc32434.c
Normal file
221
arch/mips/pci/pci-rc32434.c
Normal file
@ -0,0 +1,221 @@
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/*
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* BRIEF MODULE DESCRIPTION
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* PCI initialization for IDT EB434 board
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*
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* Copyright 2004 IDT Inc. (rischelp@idt.com)
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
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|
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
|
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|
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#include <asm/mach-rc32434/rc32434.h>
|
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#include <asm/mach-rc32434/pci.h>
|
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|
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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/* define an unsigned array for the PCI registers */
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static unsigned int korina_cnfg_regs[25] = {
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KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
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KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
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KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
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KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
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KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
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KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
|
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};
|
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static struct resource rc32434_res_pci_mem1;
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static struct resource rc32434_res_pci_mem2;
|
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|
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static struct resource rc32434_res_pci_mem1 = {
|
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.name = "PCI MEM1",
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.start = 0x50000000,
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.end = 0x5FFFFFFF,
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.flags = IORESOURCE_MEM,
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.parent = &rc32434_res_pci_mem1,
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.sibling = NULL,
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.child = &rc32434_res_pci_mem2
|
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};
|
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static struct resource rc32434_res_pci_mem2 = {
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.name = "PCI Mem2",
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.start = 0x60000000,
|
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.end = 0x6FFFFFFF,
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.flags = IORESOURCE_MEM,
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.parent = &rc32434_res_pci_mem1,
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.sibling = NULL,
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.child = NULL
|
||||
};
|
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|
||||
static struct resource rc32434_res_pci_io1 = {
|
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.name = "PCI I/O1",
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.start = 0x18800000,
|
||||
.end = 0x188FFFFF,
|
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.flags = IORESOURCE_IO,
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};
|
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|
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extern struct pci_ops rc32434_pci_ops;
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|
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#define PCI_MEM1_START PCI_ADDR_START
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#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
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#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
|
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#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
|
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#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
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#define PCI_IO1_END \
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(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
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#define PCI_IO2_START \
|
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(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
|
||||
#define PCI_IO2_END \
|
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(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
|
||||
|
||||
struct pci_controller rc32434_controller2;
|
||||
|
||||
struct pci_controller rc32434_controller = {
|
||||
.pci_ops = &rc32434_pci_ops,
|
||||
.mem_resource = &rc32434_res_pci_mem1,
|
||||
.io_resource = &rc32434_res_pci_io1,
|
||||
.mem_offset = 0,
|
||||
.io_offset = 0,
|
||||
|
||||
};
|
||||
|
||||
#ifdef __MIPSEB__
|
||||
#define PCI_ENDIAN_FLAG PCILBAC_sb_m
|
||||
#else
|
||||
#define PCI_ENDIAN_FLAG 0
|
||||
#endif
|
||||
|
||||
static int __init rc32434_pcibridge_init(void)
|
||||
{
|
||||
unsigned int pcicvalue, pcicdata = 0;
|
||||
unsigned int dummyread, pcicntlval;
|
||||
int loopCount;
|
||||
unsigned int pci_config_addr;
|
||||
|
||||
pcicvalue = rc32434_pci->pcic;
|
||||
pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
|
||||
if (!((pcicvalue == PCIM_H_EA) ||
|
||||
(pcicvalue == PCIM_H_IA_FIX) ||
|
||||
(pcicvalue == PCIM_H_IA_RR))) {
|
||||
pr_err(KERN_ERR "PCI init error!!!\n");
|
||||
/* Not in Host Mode, return ERROR */
|
||||
return -1;
|
||||
}
|
||||
/* Enables the Idle Grant mode, Arbiter Parking */
|
||||
pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
|
||||
rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */
|
||||
/* Zero out the PCI status & PCI Status Mask */
|
||||
for (;;) {
|
||||
pcicdata = rc32434_pci->pcis;
|
||||
if (!(pcicdata & PCI_STAT_RIP))
|
||||
break;
|
||||
}
|
||||
|
||||
rc32434_pci->pcis = 0;
|
||||
rc32434_pci->pcism = 0xFFFFFFFF;
|
||||
/* Zero out the PCI decoupled registers */
|
||||
rc32434_pci->pcidac = 0; /*
|
||||
* disable PCI decoupled accesses at
|
||||
* initialization
|
||||
*/
|
||||
rc32434_pci->pcidas = 0; /* clear the status */
|
||||
rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */
|
||||
/* Mask PCI Messaging Interrupts */
|
||||
rc32434_pci_msg->pciiic = 0;
|
||||
rc32434_pci_msg->pciiim = 0xFFFFFFFF;
|
||||
rc32434_pci_msg->pciioic = 0;
|
||||
rc32434_pci_msg->pciioim = 0;
|
||||
|
||||
|
||||
/* Setup PCILB0 as Memory Window */
|
||||
rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
|
||||
|
||||
/* setup the PCI map address as same as the local address */
|
||||
|
||||
rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
|
||||
|
||||
|
||||
/* Setup PCILBA1 as MEM */
|
||||
rc32434_pci->pcilba[0].control =
|
||||
(((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
|
||||
dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
|
||||
rc32434_pci->pcilba[1].address = 0x60000000;
|
||||
rc32434_pci->pcilba[1].mapping = 0x60000000;
|
||||
|
||||
/* setup PCILBA2 as IO Window */
|
||||
rc32434_pci->pcilba[1].control =
|
||||
(((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
|
||||
dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
|
||||
rc32434_pci->pcilba[2].address = 0x18C00000;
|
||||
rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
|
||||
|
||||
/* setup PCILBA2 as IO Window */
|
||||
rc32434_pci->pcilba[2].control =
|
||||
(((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
|
||||
dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
|
||||
|
||||
/* Setup PCILBA3 as IO Window */
|
||||
rc32434_pci->pcilba[3].address = 0x18800000;
|
||||
rc32434_pci->pcilba[3].mapping = 0x18800000;
|
||||
rc32434_pci->pcilba[3].control =
|
||||
((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
|
||||
PCI_ENDIAN_FLAG);
|
||||
dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
|
||||
|
||||
pci_config_addr = (unsigned int) (0x80000004);
|
||||
for (loopCount = 0; loopCount < 24; loopCount++) {
|
||||
rc32434_pci->pcicfga = pci_config_addr;
|
||||
dummyread = rc32434_pci->pcicfga;
|
||||
rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
|
||||
dummyread = rc32434_pci->pcicfgd;
|
||||
pci_config_addr += 4;
|
||||
}
|
||||
rc32434_pci->pcitc =
|
||||
(unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
|
||||
((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
|
||||
|
||||
pcicntlval = rc32434_pci->pcic;
|
||||
pcicntlval &= ~PCI_CTL_TNR;
|
||||
rc32434_pci->pcic = pcicntlval;
|
||||
pcicntlval = rc32434_pci->pcic;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init rc32434_pci_init(void)
|
||||
{
|
||||
pr_info("PCI: Initializing PCI\n");
|
||||
|
||||
ioport_resource.start = rc32434_res_pci_io1.start;
|
||||
ioport_resource.end = rc32434_res_pci_io1.end;
|
||||
|
||||
rc32434_pcibridge_init();
|
||||
|
||||
register_pci_controller(&rc32434_controller);
|
||||
rc32434_sync();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(rc32434_pci_init);
|
||||
7
arch/mips/rb532/Makefile
Normal file
7
arch/mips/rb532/Makefile
Normal file
@ -0,0 +1,7 @@
|
||||
#
|
||||
# Makefile for the RB532 board specific parts of the kernel
|
||||
#
|
||||
|
||||
obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
|
||||
|
||||
EXTRA_CFLAGS += -Werror
|
||||
331
arch/mips/rb532/devices.c
Normal file
331
arch/mips/rb532/devices.c
Normal file
@ -0,0 +1,331 @@
|
||||
/*
|
||||
* RouterBoard 500 Platform devices
|
||||
*
|
||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
#include <asm/mach-rc32434/rc32434.h>
|
||||
#include <asm/mach-rc32434/dma.h>
|
||||
#include <asm/mach-rc32434/dma_v.h>
|
||||
#include <asm/mach-rc32434/eth.h>
|
||||
#include <asm/mach-rc32434/rb.h>
|
||||
#include <asm/mach-rc32434/integ.h>
|
||||
#include <asm/mach-rc32434/gpio.h>
|
||||
|
||||
#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
|
||||
#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
|
||||
#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
|
||||
#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
|
||||
|
||||
#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
|
||||
#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
|
||||
|
||||
/* NAND definitions */
|
||||
#define GPIO_RDY (1 << 0x08)
|
||||
#define GPIO_WPX (1 << 0x09)
|
||||
#define GPIO_ALE (1 << 0x0a)
|
||||
#define GPIO_CLE (1 << 0x0b)
|
||||
|
||||
extern char *board_type;
|
||||
|
||||
static struct resource korina_dev0_res[] = {
|
||||
{
|
||||
.name = "korina_regs",
|
||||
.start = ETH0_BASE_ADDR,
|
||||
.end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.name = "korina_rx",
|
||||
.start = ETH0_DMA_RX_IRQ,
|
||||
.end = ETH0_DMA_RX_IRQ,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}, {
|
||||
.name = "korina_tx",
|
||||
.start = ETH0_DMA_TX_IRQ,
|
||||
.end = ETH0_DMA_TX_IRQ,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}, {
|
||||
.name = "korina_ovr",
|
||||
.start = ETH0_RX_OVR_IRQ,
|
||||
.end = ETH0_RX_OVR_IRQ,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}, {
|
||||
.name = "korina_und",
|
||||
.start = ETH0_TX_UND_IRQ,
|
||||
.end = ETH0_TX_UND_IRQ,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}, {
|
||||
.name = "korina_dma_rx",
|
||||
.start = ETH0_RX_DMA_ADDR,
|
||||
.end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.name = "korina_dma_tx",
|
||||
.start = ETH0_TX_DMA_ADDR,
|
||||
.end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct korina_device korina_dev0_data = {
|
||||
.name = "korina0",
|
||||
.mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
|
||||
};
|
||||
|
||||
static struct platform_device korina_dev0 = {
|
||||
.id = 0,
|
||||
.name = "korina",
|
||||
.dev.platform_data = &korina_dev0_data,
|
||||
.resource = korina_dev0_res,
|
||||
.num_resources = ARRAY_SIZE(korina_dev0_res),
|
||||
};
|
||||
|
||||
#define CF_GPIO_NUM 13
|
||||
|
||||
static struct resource cf_slot0_res[] = {
|
||||
{
|
||||
.name = "cf_membase",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.name = "cf_irq",
|
||||
.start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
|
||||
.end = (8 + 4 * 32 + CF_GPIO_NUM),
|
||||
.flags = IORESOURCE_IRQ
|
||||
}
|
||||
};
|
||||
|
||||
static struct cf_device cf_slot0_data = {
|
||||
.gpio_pin = 13
|
||||
};
|
||||
|
||||
static struct platform_device cf_slot0 = {
|
||||
.id = 0,
|
||||
.name = "pata-rb532-cf",
|
||||
.dev.platform_data = &cf_slot0_data,
|
||||
.resource = cf_slot0_res,
|
||||
.num_resources = ARRAY_SIZE(cf_slot0_res),
|
||||
};
|
||||
|
||||
/* Resources and device for NAND */
|
||||
static int rb532_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
|
||||
}
|
||||
|
||||
static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
unsigned char orbits, nandbits;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
orbits = (ctrl & NAND_CLE) << 1;
|
||||
orbits |= (ctrl & NAND_ALE) >> 1;
|
||||
|
||||
nandbits = (~ctrl & NAND_CLE) << 1;
|
||||
nandbits |= (~ctrl & NAND_ALE) >> 1;
|
||||
|
||||
set_latch_u5(orbits, nandbits);
|
||||
}
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, chip->IO_ADDR_W);
|
||||
}
|
||||
|
||||
static struct resource nand_slot0_res[] = {
|
||||
[0] = {
|
||||
.name = "nand_membase",
|
||||
.flags = IORESOURCE_MEM
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_nand_data rb532_nand_data = {
|
||||
.ctrl.dev_ready = rb532_dev_ready,
|
||||
.ctrl.cmd_ctrl = rb532_cmd_ctrl,
|
||||
};
|
||||
|
||||
static struct platform_device nand_slot0 = {
|
||||
.name = "gen_nand",
|
||||
.id = -1,
|
||||
.resource = nand_slot0_res,
|
||||
.num_resources = ARRAY_SIZE(nand_slot0_res),
|
||||
.dev.platform_data = &rb532_nand_data,
|
||||
};
|
||||
|
||||
static struct mtd_partition rb532_partition_info[] = {
|
||||
{
|
||||
.name = "Routerboard NAND boot",
|
||||
.offset = 0,
|
||||
.size = 4 * 1024 * 1024,
|
||||
}, {
|
||||
.name = "rootfs",
|
||||
.offset = MTDPART_OFS_NXTBLK,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device rb532_led = {
|
||||
.name = "rb532-led",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static struct gpio_keys_button rb532_gpio_btn[] = {
|
||||
{
|
||||
.gpio = 1,
|
||||
.code = BTN_0,
|
||||
.desc = "S1",
|
||||
.active_low = 1,
|
||||
}
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data rb532_gpio_btn_data = {
|
||||
.buttons = rb532_gpio_btn,
|
||||
.nbuttons = ARRAY_SIZE(rb532_gpio_btn),
|
||||
};
|
||||
|
||||
static struct platform_device rb532_button = {
|
||||
.name = "gpio-keys",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &rb532_gpio_btn_data,
|
||||
}
|
||||
};
|
||||
|
||||
static struct resource rb532_wdt_res[] = {
|
||||
{
|
||||
.name = "rb532_wdt_res",
|
||||
.start = INTEG0_BASE_ADDR,
|
||||
.end = INTEG0_BASE_ADDR + sizeof(struct integ),
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device rb532_wdt = {
|
||||
.name = "rc32434_wdt",
|
||||
.id = -1,
|
||||
.resource = rb532_wdt_res,
|
||||
.num_resources = ARRAY_SIZE(rb532_wdt_res),
|
||||
};
|
||||
|
||||
static struct platform_device *rb532_devs[] = {
|
||||
&korina_dev0,
|
||||
&nand_slot0,
|
||||
&cf_slot0,
|
||||
&rb532_led,
|
||||
&rb532_button,
|
||||
&rb532_wdt
|
||||
};
|
||||
|
||||
static void __init parse_mac_addr(char *macstr)
|
||||
{
|
||||
int i, j;
|
||||
unsigned char result, value;
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
result = 0;
|
||||
|
||||
if (i != 5 && *(macstr + 2) != ':')
|
||||
return;
|
||||
|
||||
for (j = 0; j < 2; j++) {
|
||||
if (isxdigit(*macstr)
|
||||
&& (value =
|
||||
isdigit(*macstr) ? *macstr -
|
||||
'0' : toupper(*macstr) - 'A' + 10) < 16) {
|
||||
result = result * 16 + value;
|
||||
macstr++;
|
||||
} else
|
||||
return;
|
||||
}
|
||||
|
||||
macstr++;
|
||||
korina_dev0_data.mac[i] = result;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* DEVICE CONTROLLER 1 */
|
||||
#define CFG_DC_DEV1 ((void *)0xb8010010)
|
||||
#define CFG_DC_DEV2 ((void *)0xb8010020)
|
||||
#define CFG_DC_DEVBASE 0x0
|
||||
#define CFG_DC_DEVMASK 0x4
|
||||
#define CFG_DC_DEVC 0x8
|
||||
#define CFG_DC_DEVTC 0xC
|
||||
|
||||
/* NAND definitions */
|
||||
#define NAND_CHIP_DELAY 25
|
||||
|
||||
static void __init rb532_nand_setup(void)
|
||||
{
|
||||
switch (mips_machtype) {
|
||||
case MACH_MIKROTIK_RB532A:
|
||||
set_latch_u5(LO_FOFF | LO_CEX,
|
||||
LO_ULED | LO_ALE | LO_CLE | LO_WPX);
|
||||
break;
|
||||
default:
|
||||
set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
|
||||
LO_ULED | LO_ALE | LO_CLE);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Setup NAND specific settings */
|
||||
rb532_nand_data.chip.nr_chips = 1;
|
||||
rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
|
||||
rb532_nand_data.chip.partitions = rb532_partition_info;
|
||||
rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
|
||||
rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
|
||||
}
|
||||
|
||||
|
||||
static int __init plat_setup_devices(void)
|
||||
{
|
||||
/* Look for the CF card reader */
|
||||
if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
|
||||
rb532_devs[1] = NULL;
|
||||
else {
|
||||
cf_slot0_res[0].start =
|
||||
readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
|
||||
cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
|
||||
}
|
||||
|
||||
/* Read the NAND resources from the device controller */
|
||||
nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
|
||||
nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
|
||||
|
||||
/* Initialise the NAND device */
|
||||
rb532_nand_setup();
|
||||
|
||||
return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
|
||||
}
|
||||
|
||||
static int __init setup_kmac(char *s)
|
||||
{
|
||||
printk(KERN_INFO "korina mac = %s\n", s);
|
||||
parse_mac_addr(s);
|
||||
return 0;
|
||||
}
|
||||
|
||||
__setup("kmac=", setup_kmac);
|
||||
|
||||
arch_initcall(plat_setup_devices);
|
||||
220
arch/mips/rb532/gpio.c
Normal file
220
arch/mips/rb532/gpio.c
Normal file
@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Miscellaneous functions for IDT EB434 board
|
||||
*
|
||||
* Copyright 2004 IDT Inc. (rischelp@idt.com)
|
||||
* Copyright 2006 Phil Sutter <n0-1@freewrt.org>
|
||||
* Copyright 2007 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#include <asm/mach-rc32434/rb.h>
|
||||
|
||||
struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
|
||||
EXPORT_SYMBOL(rb532_gpio_reg0);
|
||||
|
||||
struct mpmc_device dev3;
|
||||
|
||||
static struct resource rb532_gpio_reg0_res[] = {
|
||||
{
|
||||
.name = "gpio_reg0",
|
||||
.start = (u32)(IDT434_REG_BASE + GPIOBASE),
|
||||
.end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct resource rb532_dev3_ctl_res[] = {
|
||||
{
|
||||
.name = "dev3_ctl",
|
||||
.start = (u32)(IDT434_REG_BASE + DEV3BASE),
|
||||
.end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
|
||||
{
|
||||
unsigned flags, data;
|
||||
unsigned i = 0;
|
||||
|
||||
spin_lock_irqsave(&dev3.lock, flags);
|
||||
|
||||
data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
|
||||
for (i = 0; i != len; ++i) {
|
||||
if (val & (1 << i))
|
||||
data |= (1 << (i + bit));
|
||||
else
|
||||
data &= ~(1 << (i + bit));
|
||||
}
|
||||
writel(data, (IDT434_REG_BASE + reg_offs));
|
||||
|
||||
spin_unlock_irqrestore(&dev3.lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(set_434_reg);
|
||||
|
||||
unsigned get_434_reg(unsigned reg_offs)
|
||||
{
|
||||
return readl(IDT434_REG_BASE + reg_offs);
|
||||
}
|
||||
EXPORT_SYMBOL(get_434_reg);
|
||||
|
||||
void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
|
||||
{
|
||||
unsigned flags;
|
||||
|
||||
spin_lock_irqsave(&dev3.lock, flags);
|
||||
|
||||
dev3.state = (dev3.state | or_mask) & ~nand_mask;
|
||||
writel(dev3.state, &dev3.base);
|
||||
|
||||
spin_unlock_irqrestore(&dev3.lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(set_latch_u5);
|
||||
|
||||
unsigned char get_latch_u5(void)
|
||||
{
|
||||
return dev3.state;
|
||||
}
|
||||
EXPORT_SYMBOL(get_latch_u5);
|
||||
|
||||
int rb532_gpio_get_value(unsigned gpio)
|
||||
{
|
||||
return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_get_value);
|
||||
|
||||
void rb532_gpio_set_value(unsigned gpio, int value)
|
||||
{
|
||||
unsigned tmp;
|
||||
|
||||
tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
|
||||
if (value)
|
||||
tmp |= 1 << gpio;
|
||||
|
||||
writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_set_value);
|
||||
|
||||
int rb532_gpio_direction_input(unsigned gpio)
|
||||
{
|
||||
writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
|
||||
(void *)&rb532_gpio_reg0->gpiocfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_direction_input);
|
||||
|
||||
int rb532_gpio_direction_output(unsigned gpio, int value)
|
||||
{
|
||||
gpio_set_value(gpio, value);
|
||||
writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
|
||||
(void *)&rb532_gpio_reg0->gpiocfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_direction_output);
|
||||
|
||||
void rb532_gpio_set_int_level(unsigned gpio, int value)
|
||||
{
|
||||
unsigned tmp;
|
||||
|
||||
tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
|
||||
if (value)
|
||||
tmp |= 1 << gpio;
|
||||
writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_set_int_level);
|
||||
|
||||
int rb532_gpio_get_int_level(unsigned gpio)
|
||||
{
|
||||
return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_get_int_level);
|
||||
|
||||
void rb532_gpio_set_int_status(unsigned gpio, int value)
|
||||
{
|
||||
unsigned tmp;
|
||||
|
||||
tmp = readl(&rb532_gpio_reg0->gpioistat);
|
||||
if (value)
|
||||
tmp |= 1 << gpio;
|
||||
writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_set_int_status);
|
||||
|
||||
int rb532_gpio_get_int_status(unsigned gpio)
|
||||
{
|
||||
return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_get_int_status);
|
||||
|
||||
void rb532_gpio_set_func(unsigned gpio, int value)
|
||||
{
|
||||
unsigned tmp;
|
||||
|
||||
tmp = readl(&rb532_gpio_reg0->gpiofunc);
|
||||
if (value)
|
||||
tmp |= 1 << gpio;
|
||||
writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_set_func);
|
||||
|
||||
int rb532_gpio_get_func(unsigned gpio)
|
||||
{
|
||||
return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_get_func);
|
||||
|
||||
int __init rb532_gpio_init(void)
|
||||
{
|
||||
rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
|
||||
rb532_gpio_reg0_res[0].end -
|
||||
rb532_gpio_reg0_res[0].start);
|
||||
|
||||
if (!rb532_gpio_reg0) {
|
||||
printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
|
||||
rb532_dev3_ctl_res[0].end -
|
||||
rb532_dev3_ctl_res[0].start);
|
||||
|
||||
if (!dev3.base) {
|
||||
printk(KERN_ERR "rb532: cannot remap device controller 3\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(rb532_gpio_init);
|
||||
209
arch/mips/rb532/irq.c
Normal file
209
arch/mips/rb532/irq.c
Normal file
@ -0,0 +1,209 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
* Copyright 2002 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* stevel@mvista.com or source@mvista.com
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
#include <asm/mach-rc32434/rc32434.h>
|
||||
|
||||
struct intr_group {
|
||||
u32 mask; /* mask of valid bits in pending/mask registers */
|
||||
volatile u32 *base_addr;
|
||||
};
|
||||
|
||||
#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
|
||||
|
||||
#if (NR_IRQS < RC32434_NR_IRQS)
|
||||
#error Too little irqs defined. Did you override <asm/irq.h> ?
|
||||
#endif
|
||||
|
||||
static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
|
||||
{
|
||||
.mask = 0x0000efff,
|
||||
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
|
||||
{
|
||||
.mask = 0x00001fff,
|
||||
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
|
||||
{
|
||||
.mask = 0x00000007,
|
||||
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
|
||||
{
|
||||
.mask = 0x0003ffff,
|
||||
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
|
||||
{
|
||||
.mask = 0xffffffff,
|
||||
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
|
||||
};
|
||||
|
||||
#define READ_PEND(base) (*(base))
|
||||
#define READ_MASK(base) (*(base + 2))
|
||||
#define WRITE_MASK(base, val) (*(base + 2) = (val))
|
||||
|
||||
static inline int irq_to_group(unsigned int irq_nr)
|
||||
{
|
||||
return (irq_nr - GROUP0_IRQ_BASE) >> 5;
|
||||
}
|
||||
|
||||
static inline int group_to_ip(unsigned int group)
|
||||
{
|
||||
return group + 2;
|
||||
}
|
||||
|
||||
static inline void enable_local_irq(unsigned int ip)
|
||||
{
|
||||
int ipnum = 0x100 << ip;
|
||||
|
||||
set_c0_status(ipnum);
|
||||
}
|
||||
|
||||
static inline void disable_local_irq(unsigned int ip)
|
||||
{
|
||||
int ipnum = 0x100 << ip;
|
||||
|
||||
clear_c0_status(ipnum);
|
||||
}
|
||||
|
||||
static inline void ack_local_irq(unsigned int ip)
|
||||
{
|
||||
int ipnum = 0x100 << ip;
|
||||
|
||||
clear_c0_cause(ipnum);
|
||||
}
|
||||
|
||||
static void rb532_enable_irq(unsigned int irq_nr)
|
||||
{
|
||||
int ip = irq_nr - GROUP0_IRQ_BASE;
|
||||
unsigned int group, intr_bit;
|
||||
volatile unsigned int *addr;
|
||||
|
||||
if (ip < 0)
|
||||
enable_local_irq(irq_nr);
|
||||
else {
|
||||
group = ip >> 5;
|
||||
|
||||
ip &= (1 << 5) - 1;
|
||||
intr_bit = 1 << ip;
|
||||
|
||||
enable_local_irq(group_to_ip(group));
|
||||
|
||||
addr = intr_group[group].base_addr;
|
||||
WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
|
||||
}
|
||||
}
|
||||
|
||||
static void rb532_disable_irq(unsigned int irq_nr)
|
||||
{
|
||||
int ip = irq_nr - GROUP0_IRQ_BASE;
|
||||
unsigned int group, intr_bit, mask;
|
||||
volatile unsigned int *addr;
|
||||
|
||||
if (ip < 0) {
|
||||
disable_local_irq(irq_nr);
|
||||
} else {
|
||||
group = ip >> 5;
|
||||
|
||||
ip &= (1 << 5) - 1;
|
||||
intr_bit = 1 << ip;
|
||||
addr = intr_group[group].base_addr;
|
||||
mask = READ_MASK(addr);
|
||||
mask |= intr_bit;
|
||||
WRITE_MASK(addr, mask);
|
||||
|
||||
/*
|
||||
* if there are no more interrupts enabled in this
|
||||
* group, disable corresponding IP
|
||||
*/
|
||||
if (mask == intr_group[group].mask)
|
||||
disable_local_irq(group_to_ip(group));
|
||||
}
|
||||
}
|
||||
|
||||
static void rb532_mask_and_ack_irq(unsigned int irq_nr)
|
||||
{
|
||||
rb532_disable_irq(irq_nr);
|
||||
ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
|
||||
}
|
||||
|
||||
static struct irq_chip rc32434_irq_type = {
|
||||
.name = "RB532",
|
||||
.ack = rb532_disable_irq,
|
||||
.mask = rb532_disable_irq,
|
||||
.mask_ack = rb532_mask_and_ack_irq,
|
||||
.unmask = rb532_enable_irq,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
|
||||
|
||||
for (i = 0; i < RC32434_NR_IRQS; i++)
|
||||
set_irq_chip_and_handler(i, &rc32434_irq_type,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
/* Main Interrupt dispatcher */
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int ip, pend, group;
|
||||
volatile unsigned int *addr;
|
||||
unsigned int cp0_cause = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (cp0_cause & CAUSEF_IP7) {
|
||||
do_IRQ(7);
|
||||
} else {
|
||||
ip = (cp0_cause & 0x7c00);
|
||||
if (ip) {
|
||||
group = 21 + (fls(ip) - 32);
|
||||
|
||||
addr = intr_group[group].base_addr;
|
||||
|
||||
pend = READ_PEND(addr);
|
||||
pend &= ~READ_MASK(addr); /* only unmasked interrupts */
|
||||
pend = 39 + (fls(pend) - 32);
|
||||
do_IRQ((group << 5) + pend);
|
||||
}
|
||||
}
|
||||
}
|
||||
158
arch/mips/rb532/prom.c
Normal file
158
arch/mips/rb532/prom.c
Normal file
@ -0,0 +1,158 @@
|
||||
/*
|
||||
* RouterBoard 500 specific prom routines
|
||||
*
|
||||
* Copyright (C) 2003, Peter Sadik <peter.sadik@idt.com>
|
||||
* Copyright (C) 2005-2006, P.Christeas <p_christ@hol.gr>
|
||||
* Copyright (C) 2007, Gabor Juhos <juhosg@openwrt.org>
|
||||
* Felix Fietkau <nbd@openwrt.org>
|
||||
* Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/blkdev.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/mach-rc32434/ddr.h>
|
||||
#include <asm/mach-rc32434/prom.h>
|
||||
|
||||
extern void __init setup_serial_port(void);
|
||||
|
||||
unsigned int idt_cpu_freq = 132000000;
|
||||
EXPORT_SYMBOL(idt_cpu_freq);
|
||||
unsigned int gpio_bootup_state;
|
||||
EXPORT_SYMBOL(gpio_bootup_state);
|
||||
|
||||
static struct resource ddr_reg[] = {
|
||||
{
|
||||
.name = "ddr-reg",
|
||||
.start = DDR0_PHYS_ADDR,
|
||||
.end = DDR0_PHYS_ADDR + sizeof(struct ddr_ram),
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
/* No prom memory to free */
|
||||
}
|
||||
|
||||
static inline int match_tag(char *arg, const char *tag)
|
||||
{
|
||||
return strncmp(arg, tag, strlen(tag)) == 0;
|
||||
}
|
||||
|
||||
static inline unsigned long tag2ul(char *arg, const char *tag)
|
||||
{
|
||||
char *num;
|
||||
|
||||
num = arg + strlen(tag);
|
||||
return simple_strtoul(num, 0, 10);
|
||||
}
|
||||
|
||||
void __init prom_setup_cmdline(void)
|
||||
{
|
||||
char cmd_line[CL_SIZE];
|
||||
char *cp, *board;
|
||||
int prom_argc;
|
||||
char **prom_argv, **prom_envp;
|
||||
int i;
|
||||
|
||||
prom_argc = fw_arg0;
|
||||
prom_argv = (char **) fw_arg1;
|
||||
prom_envp = (char **) fw_arg2;
|
||||
|
||||
cp = cmd_line;
|
||||
/* Note: it is common that parameters start
|
||||
* at argv[1] and not argv[0],
|
||||
* however, our elf loader starts at [0] */
|
||||
for (i = 0; i < prom_argc; i++) {
|
||||
if (match_tag(prom_argv[i], FREQ_TAG)) {
|
||||
idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG);
|
||||
continue;
|
||||
}
|
||||
#ifdef IGNORE_CMDLINE_MEM
|
||||
/* parses out the "mem=xx" arg */
|
||||
if (match_tag(prom_argv[i], MEM_TAG))
|
||||
continue;
|
||||
#endif
|
||||
if (i > 0)
|
||||
*(cp++) = ' ';
|
||||
if (match_tag(prom_argv[i], BOARD_TAG)) {
|
||||
board = prom_argv[i] + strlen(BOARD_TAG);
|
||||
|
||||
if (match_tag(board, BOARD_RB532A))
|
||||
mips_machtype = MACH_MIKROTIK_RB532A;
|
||||
else
|
||||
mips_machtype = MACH_MIKROTIK_RB532;
|
||||
}
|
||||
|
||||
if (match_tag(prom_argv[i], GPIO_TAG))
|
||||
gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
|
||||
|
||||
strcpy(cp, prom_argv[i]);
|
||||
cp += strlen(prom_argv[i]);
|
||||
}
|
||||
*(cp++) = ' ';
|
||||
|
||||
i = strlen(arcs_cmdline);
|
||||
if (i > 0) {
|
||||
*(cp++) = ' ';
|
||||
strcpy(cp, arcs_cmdline);
|
||||
cp += strlen(arcs_cmdline);
|
||||
}
|
||||
if (gpio_bootup_state & 0x02)
|
||||
strcpy(cp, GPIO_INIT_NOBUTTON);
|
||||
else
|
||||
strcpy(cp, GPIO_INIT_BUTTON);
|
||||
|
||||
cmd_line[CL_SIZE-1] = '\0';
|
||||
|
||||
strcpy(arcs_cmdline, cmd_line);
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
struct ddr_ram __iomem *ddr;
|
||||
phys_t memsize;
|
||||
phys_t ddrbase;
|
||||
|
||||
ddr = ioremap_nocache(ddr_reg[0].start,
|
||||
ddr_reg[0].end - ddr_reg[0].start);
|
||||
|
||||
if (!ddr) {
|
||||
printk(KERN_ERR "Unable to remap DDR register\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ddrbase = (phys_t)&ddr->ddrbase;
|
||||
memsize = (phys_t)&ddr->ddrmask;
|
||||
memsize = 0 - memsize;
|
||||
|
||||
prom_setup_cmdline();
|
||||
|
||||
/* give all RAM to boot allocator,
|
||||
* except for the first 0x400 and the last 0x200 bytes */
|
||||
add_memory_region(ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
|
||||
}
|
||||
53
arch/mips/rb532/serial.c
Normal file
53
arch/mips/rb532/serial.c
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Serial port initialisation.
|
||||
*
|
||||
* Copyright 2004 IDT Inc. (rischelp@idt.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_8250.h>
|
||||
|
||||
#include <asm/serial.h>
|
||||
#include <asm/mach-rc32434/rc32434.h>
|
||||
|
||||
extern unsigned int idt_cpu_freq;
|
||||
|
||||
static struct uart_port rb532_uart = {
|
||||
.type = PORT_16550A,
|
||||
.line = 0,
|
||||
.irq = RC32434_UART0_IRQ,
|
||||
.iotype = UPIO_MEM,
|
||||
.membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
|
||||
.regshift = 2
|
||||
};
|
||||
|
||||
int __init setup_serial_port(void)
|
||||
{
|
||||
rb532_uart.uartclk = idt_cpu_freq;
|
||||
|
||||
return early_serial_setup(&rb532_uart);
|
||||
}
|
||||
arch_initcall(setup_serial_port);
|
||||
79
arch/mips/rb532/setup.c
Normal file
79
arch/mips/rb532/setup.c
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* setup.c - boot time setup code
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <asm/mach-rc32434/rc32434.h>
|
||||
#include <asm/mach-rc32434/pci.h>
|
||||
|
||||
struct pci_reg __iomem *pci_reg;
|
||||
EXPORT_SYMBOL(pci_reg);
|
||||
|
||||
static struct resource pci0_res[] = {
|
||||
{
|
||||
.name = "pci_reg0",
|
||||
.start = PCI0_BASE_ADDR,
|
||||
.end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static void rb_machine_restart(char *command)
|
||||
{
|
||||
/* just jump to the reset vector */
|
||||
writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
|
||||
((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
|
||||
}
|
||||
|
||||
static void rb_machine_halt(void)
|
||||
{
|
||||
for (;;)
|
||||
continue;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
_machine_restart = rb_machine_restart;
|
||||
_machine_halt = rb_machine_halt;
|
||||
pm_power_off = rb_machine_halt;
|
||||
|
||||
set_io_port_base(KSEG1);
|
||||
|
||||
pci_reg = ioremap_nocache(pci0_res[0].start,
|
||||
pci0_res[0].end - pci0_res[0].start);
|
||||
if (!pci_reg) {
|
||||
printk(KERN_ERR "Could not remap PCI registers\n");
|
||||
return;
|
||||
}
|
||||
|
||||
val = __raw_readl(&pci_reg->pcic);
|
||||
val &= 0xFFFFFF7;
|
||||
__raw_writel(val, (void *)&pci_reg->pcic);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* Enable PCI interrupts in EPLD Mask register */
|
||||
*epld_mask = 0x0;
|
||||
*(epld_mask + 1) = 0x0;
|
||||
#endif
|
||||
write_c0_wired(0);
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
switch (mips_machtype) {
|
||||
case MACH_MIKROTIK_RB532A:
|
||||
return "Mikrotik RB532A";
|
||||
break;
|
||||
default:
|
||||
return "Mikrotik RB532";
|
||||
break;
|
||||
}
|
||||
}
|
||||
67
arch/mips/rb532/time.c
Normal file
67
arch/mips/rb532/time.c
Normal file
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* Setting up the clock on the MIPS boards.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/timex.h>
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/debug.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/mach-rc32434/rc32434.h>
|
||||
|
||||
extern unsigned int idt_cpu_freq;
|
||||
|
||||
/*
|
||||
* Figure out the r4k offset, the amount to increment the compare
|
||||
* register for each time tick. There is no RTC available.
|
||||
*
|
||||
* The RC32434 counts at half the CPU *core* speed.
|
||||
*/
|
||||
static unsigned long __init cal_r4koff(void)
|
||||
{
|
||||
mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
|
||||
|
||||
return mips_hpt_frequency / HZ;
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
unsigned int est_freq, flags;
|
||||
unsigned long r4k_offset;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
printk(KERN_INFO "calculating r4koff... ");
|
||||
r4k_offset = cal_r4koff();
|
||||
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
|
||||
|
||||
est_freq = 2 * r4k_offset * HZ;
|
||||
est_freq += 5000; /* round */
|
||||
est_freq -= est_freq % 10000;
|
||||
printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
|
||||
(est_freq % 1000000) * 100 / 1000000);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
@ -51,6 +51,12 @@
|
||||
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
|
||||
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
|
||||
|
||||
/*
|
||||
* Valid machtype for group Mikrotik
|
||||
*/
|
||||
#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
|
||||
#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
|
||||
|
||||
#define CL_SIZE COMMAND_LINE_SIZE
|
||||
|
||||
extern char *system_type;
|
||||
|
||||
81
include/asm-mips/mach-rc32434/cpu-feature-overrides.h
Normal file
81
include/asm-mips/mach-rc32434/cpu-feature-overrides.h
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* IDT RC32434 specific CPU feature overrides
|
||||
*
|
||||
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This file was derived from: include/asm-mips/cpu-features.h
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle
|
||||
* Copyright (C) 2004 Maciej W. Rozycki
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
/*
|
||||
* The IDT RC32434 SOC has a built-in MIPS 4Kc core.
|
||||
*/
|
||||
#define cpu_has_tlb 1
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_3k_cache 0
|
||||
#define cpu_has_4k_cache 1
|
||||
#define cpu_has_tx39_cache 0
|
||||
#define cpu_has_sb1_cache 0
|
||||
#define cpu_has_fpu 0
|
||||
#define cpu_has_32fpr 0
|
||||
#define cpu_has_counter 1
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_has_divec 1
|
||||
#define cpu_has_vce 0
|
||||
#define cpu_has_cache_cdex_p 0
|
||||
#define cpu_has_cache_cdex_s 0
|
||||
#define cpu_has_prefetch 1
|
||||
#define cpu_has_mcheck 1
|
||||
#define cpu_has_ejtag 1
|
||||
#define cpu_has_llsc 1
|
||||
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_mdmx 0
|
||||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_smartmips 0
|
||||
|
||||
#define cpu_has_vtag_icache 0
|
||||
/* #define cpu_has_dc_aliases ? */
|
||||
/* #define cpu_has_ic_fills_f_dc ? */
|
||||
/* #define cpu_has_pindexed_dcache ? */
|
||||
|
||||
/* #define cpu_icache_snoops_remote_store ? */
|
||||
|
||||
#define cpu_has_mips32r1 1
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_mipsmt 0
|
||||
|
||||
/* #define cpu_has_nofpuex ? */
|
||||
#define cpu_has_64bits 0
|
||||
#define cpu_has_64bit_zero_reg 0
|
||||
#define cpu_has_64bit_gp_regs 0
|
||||
#define cpu_has_64bit_addresses 0
|
||||
|
||||
#define cpu_has_inclusive_pcaches 0
|
||||
|
||||
#define cpu_dcache_line_size() 16
|
||||
#define cpu_icache_line_size() 16
|
||||
|
||||
#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
|
||||
141
include/asm-mips/mach-rc32434/ddr.h
Normal file
141
include/asm-mips/mach-rc32434/ddr.h
Normal file
@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Definitions for the DDR registers
|
||||
*
|
||||
* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
|
||||
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ASM_RC32434_DDR_H_
|
||||
#define _ASM_RC32434_DDR_H_
|
||||
|
||||
#include <asm/mach-rc32434/rb.h>
|
||||
|
||||
/* DDR register structure */
|
||||
struct ddr_ram {
|
||||
u32 ddrbase;
|
||||
u32 ddrmask;
|
||||
u32 res1;
|
||||
u32 res2;
|
||||
u32 ddrc;
|
||||
u32 ddrabase;
|
||||
u32 ddramask;
|
||||
u32 ddramap;
|
||||
u32 ddrcust;
|
||||
u32 ddrrdc;
|
||||
u32 ddrspare;
|
||||
};
|
||||
|
||||
#define DDR0_PHYS_ADDR 0x18018000
|
||||
|
||||
/* DDR banks masks */
|
||||
#define DDR_MASK 0xffff0000
|
||||
#define DDR0_BASE_MSK DDR_MASK
|
||||
#define DDR1_BASE_MSK DDR_MASK
|
||||
|
||||
/* DDR bank0 registers */
|
||||
#define RC32434_DDR0_ATA_BIT 5
|
||||
#define RC32434_DDR0_ATA_MSK 0x000000E0
|
||||
#define RC32434_DDR0_DBW_BIT 8
|
||||
#define RC32434_DDR0_DBW_MSK 0x00000100
|
||||
#define RC32434_DDR0_WR_BIT 9
|
||||
#define RC32434_DDR0_WR_MSK 0x00000600
|
||||
#define RC32434_DDR0_PS_BIT 11
|
||||
#define RC32434_DDR0_PS_MSK 0x00001800
|
||||
#define RC32434_DDR0_DTYPE_BIT 13
|
||||
#define RC32434_DDR0_DTYPE_MSK 0x0000e000
|
||||
#define RC32434_DDR0_RFC_BIT 16
|
||||
#define RC32434_DDR0_RFC_MSK 0x000f0000
|
||||
#define RC32434_DDR0_RP_BIT 20
|
||||
#define RC32434_DDR0_RP_MSK 0x00300000
|
||||
#define RC32434_DDR0_AP_BIT 22
|
||||
#define RC32434_DDR0_AP_MSK 0x00400000
|
||||
#define RC32434_DDR0_RCD_BIT 23
|
||||
#define RC32434_DDR0_RCD_MSK 0x01800000
|
||||
#define RC32434_DDR0_CL_BIT 25
|
||||
#define RC32434_DDR0_CL_MSK 0x06000000
|
||||
#define RC32434_DDR0_DBM_BIT 27
|
||||
#define RC32434_DDR0_DBM_MSK 0x08000000
|
||||
#define RC32434_DDR0_SDS_BIT 28
|
||||
#define RC32434_DDR0_SDS_MSK 0x10000000
|
||||
#define RC32434_DDR0_ATP_BIT 29
|
||||
#define RC32434_DDR0_ATP_MSK 0x60000000
|
||||
#define RC32434_DDR0_RE_BIT 31
|
||||
#define RC32434_DDR0_RE_MSK 0x80000000
|
||||
|
||||
/* DDR bank C registers */
|
||||
#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x)
|
||||
#define RC32434_DDRC_CES_BIT 0
|
||||
#define RC32434_DDRC_ACE_BIT 1
|
||||
|
||||
/* Custom DDR bank registers */
|
||||
#define RC32434_DCST_MSK(x) BIT_TO_MASK(x)
|
||||
#define RC32434_DCST_CS_BIT 0
|
||||
#define RC32434_DCST_CS_MSK 0x00000003
|
||||
#define RC32434_DCST_WE_BIT 2
|
||||
#define RC32434_DCST_RAS_BIT 3
|
||||
#define RC32434_DCST_CAS_BIT 4
|
||||
#define RC32434_DSCT_CKE_BIT 5
|
||||
#define RC32434_DSCT_BA_BIT 6
|
||||
#define RC32434_DSCT_BA_MSK 0x000000c0
|
||||
|
||||
/* DDR QSC registers */
|
||||
#define RC32434_QSC_DM_BIT 0
|
||||
#define RC32434_QSC_DM_MSK 0x00000003
|
||||
#define RC32434_QSC_DQSBS_BIT 2
|
||||
#define RC32434_QSC_DQSBS_MSK 0x000000fc
|
||||
#define RC32434_QSC_DB_BIT 8
|
||||
#define RC32434_QSC_DB_MSK 0x00000100
|
||||
#define RC32434_QSC_DBSP_BIT 9
|
||||
#define RC32434_QSC_DBSP_MSK 0x01fffe00
|
||||
#define RC32434_QSC_BDP_BIT 25
|
||||
#define RC32434_QSC_BDP_MSK 0x7e000000
|
||||
|
||||
/* DDR LLC registers */
|
||||
#define RC32434_LLC_EAO_BIT 0
|
||||
#define RC32434_LLC_EAO_MSK 0x00000001
|
||||
#define RC32434_LLC_EO_BIT 1
|
||||
#define RC32434_LLC_EO_MSK 0x0000003e
|
||||
#define RC32434_LLC_FS_BIT 6
|
||||
#define RC32434_LLC_FS_MSK 0x000000c0
|
||||
#define RC32434_LLC_AS_BIT 8
|
||||
#define RC32434_LLC_AS_MSK 0x00000700
|
||||
#define RC32434_LLC_SP_BIT 11
|
||||
#define RC32434_LLC_SP_MSK 0x001ff800
|
||||
|
||||
/* DDR LLFC registers */
|
||||
#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x)
|
||||
#define RC32434_LLFC_MEN_BIT 0
|
||||
#define RC32434_LLFC_EAN_BIT 1
|
||||
#define RC32434_LLFC_FF_BIT 2
|
||||
|
||||
/* DDR DLLTA registers */
|
||||
#define RC32434_DLLTA_ADDR_BIT 2
|
||||
#define RC32434_DLLTA_ADDR_MSK 0xfffffffc
|
||||
|
||||
/* DDR DLLED registers */
|
||||
#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x)
|
||||
#define RC32434_DLLED_DBE_BIT 0
|
||||
#define RC32434_DLLED_DTE_BIT 1
|
||||
|
||||
#endif /* _ASM_RC32434_DDR_H_ */
|
||||
103
include/asm-mips/mach-rc32434/dma.h
Normal file
103
include/asm-mips/mach-rc32434/dma.h
Normal file
@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* DMA register definition.
|
||||
*
|
||||
* Author : ryan.holmQVist@idt.com
|
||||
* Date : 20011005
|
||||
*/
|
||||
|
||||
#ifndef __ASM_RC32434_DMA_H
|
||||
#define __ASM_RC32434_DMA_H
|
||||
|
||||
#include <asm/mach-rc32434/rb.h>
|
||||
|
||||
#define DMA0_BASE_ADDR 0x18040000
|
||||
|
||||
/*
|
||||
* DMA descriptor (in physical memory).
|
||||
*/
|
||||
|
||||
struct dma_desc {
|
||||
u32 control; /* Control. use DMAD_* */
|
||||
u32 ca; /* Current Address. */
|
||||
u32 devcs; /* Device control and status. */
|
||||
u32 link; /* Next descriptor in chain. */
|
||||
};
|
||||
|
||||
#define DMA_DESC_SIZ sizeof(struct dma_desc)
|
||||
#define DMA_DESC_COUNT_BIT 0
|
||||
#define DMA_DESC_COUNT_MSK 0x0003ffff
|
||||
#define DMA_DESC_DS_BIT 20
|
||||
#define DMA_DESC_DS_MSK 0x00300000
|
||||
|
||||
#define DMA_DESC_DEV_CMD_BIT 22
|
||||
#define DMA_DESC_DEV_CMD_MSK 0x01c00000
|
||||
|
||||
/* DMA command sizes */
|
||||
#define DMA_DESC_DEV_CMD_BYTE 0
|
||||
#define DMA_DESC_DEV_CMD_HLF_WD 1
|
||||
#define DMA_DESC_DEV_CMD_WORD 2
|
||||
#define DMA_DESC_DEV_CMD_2WORDS 3
|
||||
#define DMA_DESC_DEV_CMD_4WORDS 4
|
||||
#define DMA_DESC_DEV_CMD_6WORDS 5
|
||||
#define DMA_DESC_DEV_CMD_8WORDS 6
|
||||
#define DMA_DESC_DEV_CMD_16WORDS 7
|
||||
|
||||
/* DMA descriptors interrupts */
|
||||
#define DMA_DESC_COF (1 << 25) /* Chain on finished */
|
||||
#define DMA_DESC_COD (1 << 26) /* Chain on done */
|
||||
#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
|
||||
#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
|
||||
#define DMA_DESC_TERM (1 << 29) /* Terminated */
|
||||
#define DMA_DESC_DONE (1 << 30) /* Done */
|
||||
#define DMA_DESC_FINI (1 << 31) /* Finished */
|
||||
|
||||
/*
|
||||
* DMA register (within Internal Register Map).
|
||||
*/
|
||||
|
||||
struct dma_reg {
|
||||
u32 dmac; /* Control. */
|
||||
u32 dmas; /* Status. */
|
||||
u32 dmasm; /* Mask. */
|
||||
u32 dmadptr; /* Descriptor pointer. */
|
||||
u32 dmandptr; /* Next descriptor pointer. */
|
||||
};
|
||||
|
||||
/* DMA channels specific registers */
|
||||
#define DMA_CHAN_RUN_BIT (1 << 0)
|
||||
#define DMA_CHAN_DONE_BIT (1 << 1)
|
||||
#define DMA_CHAN_MODE_BIT (1 << 2)
|
||||
#define DMA_CHAN_MODE_MSK 0x0000000c
|
||||
#define DMA_CHAN_MODE_AUTO 0
|
||||
#define DMA_CHAN_MODE_BURST 1
|
||||
#define DMA_CHAN_MODE_XFRT 2
|
||||
#define DMA_CHAN_MODE_RSVD 3
|
||||
#define DMA_CHAN_ACT_BIT (1 << 4)
|
||||
|
||||
/* DMA status registers */
|
||||
#define DMA_STAT_FINI (1 << 0)
|
||||
#define DMA_STAT_DONE (1 << 1)
|
||||
#define DMA_STAT_CHAIN (1 << 2)
|
||||
#define DMA_STAT_ERR (1 << 3)
|
||||
#define DMA_STAT_HALT (1 << 4)
|
||||
|
||||
/*
|
||||
* DMA channel definitions
|
||||
*/
|
||||
|
||||
#define DMA_CHAN_ETH_RCV 0
|
||||
#define DMA_CHAN_ETH_XMT 1
|
||||
#define DMA_CHAN_MEM_TO_FIFO 2
|
||||
#define DMA_CHAN_FIFO_TO_MEM 3
|
||||
#define DMA_CHAN_PCI_TO_MEM 4
|
||||
#define DMA_CHAN_MEM_TO_PCI 5
|
||||
#define DMA_CHAN_COUNT 6
|
||||
|
||||
struct dma_channel {
|
||||
struct dma_reg ch[DMA_CHAN_COUNT];
|
||||
};
|
||||
|
||||
#endif /* __ASM_RC32434_DMA_H */
|
||||
52
include/asm-mips/mach-rc32434/dma_v.h
Normal file
52
include/asm-mips/mach-rc32434/dma_v.h
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* DMA register definition.
|
||||
*
|
||||
* Author : ryan.holmQVist@idt.com
|
||||
* Date : 20011005
|
||||
*/
|
||||
|
||||
#ifndef _ASM_RC32434_DMA_V_H_
|
||||
#define _ASM_RC32434_DMA_V_H_
|
||||
|
||||
#include <asm/mach-rc32434/dma.h>
|
||||
#include <asm/mach-rc32434/rc32434.h>
|
||||
|
||||
#define DMA_CHAN_OFFSET 0x14
|
||||
#define IS_DMA_USED(X) (((X) & \
|
||||
(DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
|
||||
!= 0)
|
||||
#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
|
||||
|
||||
#define DMA_HALT_TIMEOUT 500
|
||||
|
||||
static inline int rc32434_halt_dma(struct dma_reg *ch)
|
||||
{
|
||||
int timeout = 1;
|
||||
if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
|
||||
__raw_writel(0, &ch->dmac);
|
||||
for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
|
||||
if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
|
||||
__raw_writel(0, &ch->dmas);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return timeout ? 0 : 1;
|
||||
}
|
||||
|
||||
static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
|
||||
{
|
||||
__raw_writel(0, &ch->dmandptr);
|
||||
__raw_writel(dma_addr, &ch->dmadptr);
|
||||
}
|
||||
|
||||
static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
|
||||
{
|
||||
__raw_writel(dma_addr, &ch->dmandptr);
|
||||
}
|
||||
|
||||
#endif /* _ASM_RC32434_DMA_V_H_ */
|
||||
220
include/asm-mips/mach-rc32434/eth.h
Normal file
220
include/asm-mips/mach-rc32434/eth.h
Normal file
@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Definitions for the Ethernet registers
|
||||
*
|
||||
* Copyright 2002 Allend Stichter <allen.stichter@idt.com>
|
||||
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_RC32434_ETH_H
|
||||
#define __ASM_RC32434_ETH_H
|
||||
|
||||
|
||||
#define ETH0_BASE_ADDR 0x18060000
|
||||
|
||||
struct eth_regs {
|
||||
u32 ethintfc;
|
||||
u32 ethfifott;
|
||||
u32 etharc;
|
||||
u32 ethhash0;
|
||||
u32 ethhash1;
|
||||
u32 ethu0[4]; /* Reserved. */
|
||||
u32 ethpfs;
|
||||
u32 ethmcp;
|
||||
u32 eth_u1[10]; /* Reserved. */
|
||||
u32 ethspare;
|
||||
u32 eth_u2[42]; /* Reserved. */
|
||||
u32 ethsal0;
|
||||
u32 ethsah0;
|
||||
u32 ethsal1;
|
||||
u32 ethsah1;
|
||||
u32 ethsal2;
|
||||
u32 ethsah2;
|
||||
u32 ethsal3;
|
||||
u32 ethsah3;
|
||||
u32 ethrbc;
|
||||
u32 ethrpc;
|
||||
u32 ethrupc;
|
||||
u32 ethrfc;
|
||||
u32 ethtbc;
|
||||
u32 ethgpf;
|
||||
u32 eth_u9[50]; /* Reserved. */
|
||||
u32 ethmac1;
|
||||
u32 ethmac2;
|
||||
u32 ethipgt;
|
||||
u32 ethipgr;
|
||||
u32 ethclrt;
|
||||
u32 ethmaxf;
|
||||
u32 eth_u10; /* Reserved. */
|
||||
u32 ethmtest;
|
||||
u32 miimcfg;
|
||||
u32 miimcmd;
|
||||
u32 miimaddr;
|
||||
u32 miimwtd;
|
||||
u32 miimrdd;
|
||||
u32 miimind;
|
||||
u32 eth_u11; /* Reserved. */
|
||||
u32 eth_u12; /* Reserved. */
|
||||
u32 ethcfsa0;
|
||||
u32 ethcfsa1;
|
||||
u32 ethcfsa2;
|
||||
};
|
||||
|
||||
/* Ethernet interrupt registers */
|
||||
#define ETH_INT_FC_EN (1 << 0)
|
||||
#define ETH_INT_FC_ITS (1 << 1)
|
||||
#define ETH_INT_FC_RIP (1 << 2)
|
||||
#define ETH_INT_FC_JAM (1 << 3)
|
||||
#define ETH_INT_FC_OVR (1 << 4)
|
||||
#define ETH_INT_FC_UND (1 << 5)
|
||||
#define ETH_INT_FC_IOC 0x000000c0
|
||||
|
||||
/* Ethernet FIFO registers */
|
||||
#define ETH_FIFI_TT_TTH_BIT 0
|
||||
#define ETH_FIFO_TT_TTH 0x0000007f
|
||||
|
||||
/* Ethernet ARC/multicast registers */
|
||||
#define ETH_ARC_PRO (1 << 0)
|
||||
#define ETH_ARC_AM (1 << 1)
|
||||
#define ETH_ARC_AFM (1 << 2)
|
||||
#define ETH_ARC_AB (1 << 3)
|
||||
|
||||
/* Ethernet SAL registers */
|
||||
#define ETH_SAL_BYTE_5 0x000000ff
|
||||
#define ETH_SAL_BYTE_4 0x0000ff00
|
||||
#define ETH_SAL_BYTE_3 0x00ff0000
|
||||
#define ETH_SAL_BYTE_2 0xff000000
|
||||
|
||||
/* Ethernet SAH registers */
|
||||
#define ETH_SAH_BYTE1 0x000000ff
|
||||
#define ETH_SAH_BYTE0 0x0000ff00
|
||||
|
||||
/* Ethernet GPF register */
|
||||
#define ETH_GPF_PTV 0x0000ffff
|
||||
|
||||
/* Ethernet PFG register */
|
||||
#define ETH_PFS_PFD (1 << 0)
|
||||
|
||||
/* Ethernet CFSA[0-3] registers */
|
||||
#define ETH_CFSA0_CFSA4 0x000000ff
|
||||
#define ETH_CFSA0_CFSA5 0x0000ff00
|
||||
#define ETH_CFSA1_CFSA2 0x000000ff
|
||||
#define ETH_CFSA1_CFSA3 0x0000ff00
|
||||
#define ETH_CFSA1_CFSA0 0x000000ff
|
||||
#define ETH_CFSA1_CFSA1 0x0000ff00
|
||||
|
||||
/* Ethernet MAC1 registers */
|
||||
#define ETH_MAC1_RE (1 << 0)
|
||||
#define ETH_MAC1_PAF (1 << 1)
|
||||
#define ETH_MAC1_RFC (1 << 2)
|
||||
#define ETH_MAC1_TFC (1 << 3)
|
||||
#define ETH_MAC1_LB (1 << 4)
|
||||
#define ETH_MAC1_MR (1 << 31)
|
||||
|
||||
/* Ethernet MAC2 registers */
|
||||
#define ETH_MAC2_FD (1 << 0)
|
||||
#define ETH_MAC2_FLC (1 << 1)
|
||||
#define ETH_MAC2_HFE (1 << 2)
|
||||
#define ETH_MAC2_DC (1 << 3)
|
||||
#define ETH_MAC2_CEN (1 << 4)
|
||||
#define ETH_MAC2_PE (1 << 5)
|
||||
#define ETH_MAC2_VPE (1 << 6)
|
||||
#define ETH_MAC2_APE (1 << 7)
|
||||
#define ETH_MAC2_PPE (1 << 8)
|
||||
#define ETH_MAC2_LPE (1 << 9)
|
||||
#define ETH_MAC2_NB (1 << 12)
|
||||
#define ETH_MAC2_BP (1 << 13)
|
||||
#define ETH_MAC2_ED (1 << 14)
|
||||
|
||||
/* Ethernet IPGT register */
|
||||
#define ETH_IPGT 0x0000007f
|
||||
|
||||
/* Ethernet IPGR registers */
|
||||
#define ETH_IPGR_IPGR2 0x0000007f
|
||||
#define ETH_IPGR_IPGR1 0x00007f00
|
||||
|
||||
/* Ethernet CLRT registers */
|
||||
#define ETH_CLRT_MAX_RET 0x0000000f
|
||||
#define ETH_CLRT_COL_WIN 0x00003f00
|
||||
|
||||
/* Ethernet MAXF register */
|
||||
#define ETH_MAXF 0x0000ffff
|
||||
|
||||
/* Ethernet test registers */
|
||||
#define ETH_TEST_REG (1 << 2)
|
||||
#define ETH_MCP_DIV 0x000000ff
|
||||
|
||||
/* MII registers */
|
||||
#define ETH_MII_CFG_RSVD 0x0000000c
|
||||
#define ETH_MII_CMD_RD (1 << 0)
|
||||
#define ETH_MII_CMD_SCN (1 << 1)
|
||||
#define ETH_MII_REG_ADDR 0x0000001f
|
||||
#define ETH_MII_PHY_ADDR 0x00001f00
|
||||
#define ETH_MII_WTD_DATA 0x0000ffff
|
||||
#define ETH_MII_RDD_DATA 0x0000ffff
|
||||
#define ETH_MII_IND_BSY (1 << 0)
|
||||
#define ETH_MII_IND_SCN (1 << 1)
|
||||
#define ETH_MII_IND_NV (1 << 2)
|
||||
|
||||
/*
|
||||
* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
|
||||
*/
|
||||
|
||||
#define ETH_RX_FD (1 << 0)
|
||||
#define ETH_RX_LD (1 << 1)
|
||||
#define ETH_RX_ROK (1 << 2)
|
||||
#define ETH_RX_FM (1 << 3)
|
||||
#define ETH_RX_MP (1 << 4)
|
||||
#define ETH_RX_BP (1 << 5)
|
||||
#define ETH_RX_VLT (1 << 6)
|
||||
#define ETH_RX_CF (1 << 7)
|
||||
#define ETH_RX_OVR (1 << 8)
|
||||
#define ETH_RX_CRC (1 << 9)
|
||||
#define ETH_RX_CV (1 << 10)
|
||||
#define ETH_RX_DB (1 << 11)
|
||||
#define ETH_RX_LE (1 << 12)
|
||||
#define ETH_RX_LOR (1 << 13)
|
||||
#define ETH_RX_CES (1 << 14)
|
||||
#define ETH_RX_LEN_BIT 16
|
||||
#define ETH_RX_LEN 0xffff0000
|
||||
|
||||
#define ETH_TX_FD (1 << 0)
|
||||
#define ETH_TX_LD (1 << 1)
|
||||
#define ETH_TX_OEN (1 << 2)
|
||||
#define ETH_TX_PEN (1 << 3)
|
||||
#define ETH_TX_CEN (1 << 4)
|
||||
#define ETH_TX_HEN (1 << 5)
|
||||
#define ETH_TX_TOK (1 << 6)
|
||||
#define ETH_TX_MP (1 << 7)
|
||||
#define ETH_TX_BP (1 << 8)
|
||||
#define ETH_TX_UND (1 << 9)
|
||||
#define ETH_TX_OF (1 << 10)
|
||||
#define ETH_TX_ED (1 << 11)
|
||||
#define ETH_TX_EC (1 << 12)
|
||||
#define ETH_TX_LC (1 << 13)
|
||||
#define ETH_TX_TD (1 << 14)
|
||||
#define ETH_TX_CRC (1 << 15)
|
||||
#define ETH_TX_LE (1 << 16)
|
||||
#define ETH_TX_CC 0x001E0000
|
||||
|
||||
#endif /* __ASM_RC32434_ETH_H */
|
||||
126
include/asm-mips/mach-rc32434/gpio.h
Normal file
126
include/asm-mips/mach-rc32434/gpio.h
Normal file
@ -0,0 +1,126 @@
|
||||
/*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* GPIO register definition.
|
||||
*
|
||||
* Author : ryan.holmQVist@idt.com
|
||||
* Date : 20011005
|
||||
* Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
|
||||
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _RC32434_GPIO_H_
|
||||
#define _RC32434_GPIO_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct rb532_gpio_reg {
|
||||
u32 gpiofunc; /* GPIO Function Register
|
||||
* gpiofunc[x]==0 bit = gpio
|
||||
* func[x]==1 bit = altfunc
|
||||
*/
|
||||
u32 gpiocfg; /* GPIO Configuration Register
|
||||
* gpiocfg[x]==0 bit = input
|
||||
* gpiocfg[x]==1 bit = output
|
||||
*/
|
||||
u32 gpiod; /* GPIO Data Register
|
||||
* gpiod[x] read/write gpio pinX status
|
||||
*/
|
||||
u32 gpioilevel; /* GPIO Interrupt Status Register
|
||||
* interrupt level (see gpioistat)
|
||||
*/
|
||||
u32 gpioistat; /* Gpio Interrupt Status Register
|
||||
* istat[x] = (gpiod[x] == level[x])
|
||||
* cleared in ISR (STICKY bits)
|
||||
*/
|
||||
u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
|
||||
};
|
||||
|
||||
/* UART GPIO signals */
|
||||
#define RC32434_UART0_SOUT (1 << 0)
|
||||
#define RC32434_UART0_SIN (1 << 1)
|
||||
#define RC32434_UART0_RTS (1 << 2)
|
||||
#define RC32434_UART0_CTS (1 << 3)
|
||||
|
||||
/* M & P bus GPIO signals */
|
||||
#define RC32434_MP_BIT_22 (1 << 4)
|
||||
#define RC32434_MP_BIT_23 (1 << 5)
|
||||
#define RC32434_MP_BIT_24 (1 << 6)
|
||||
#define RC32434_MP_BIT_25 (1 << 7)
|
||||
|
||||
/* CPU GPIO signals */
|
||||
#define RC32434_CPU_GPIO (1 << 8)
|
||||
|
||||
/* Reserved GPIO signals */
|
||||
#define RC32434_AF_SPARE_6 (1 << 9)
|
||||
#define RC32434_AF_SPARE_4 (1 << 10)
|
||||
#define RC32434_AF_SPARE_3 (1 << 11)
|
||||
#define RC32434_AF_SPARE_2 (1 << 12)
|
||||
|
||||
/* PCI messaging unit */
|
||||
#define RC32434_PCI_MSU_GPIO (1 << 13)
|
||||
|
||||
|
||||
extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
|
||||
extern unsigned get_434_reg(unsigned reg_offs);
|
||||
extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
|
||||
extern unsigned char get_latch_u5(void);
|
||||
|
||||
extern int rb532_gpio_get_value(unsigned gpio);
|
||||
extern void rb532_gpio_set_value(unsigned gpio, int value);
|
||||
extern int rb532_gpio_direction_input(unsigned gpio);
|
||||
extern int rb532_gpio_direction_output(unsigned gpio, int value);
|
||||
extern void rb532_gpio_set_int_level(unsigned gpio, int value);
|
||||
extern int rb532_gpio_get_int_level(unsigned gpio);
|
||||
extern void rb532_gpio_set_int_status(unsigned gpio, int value);
|
||||
extern int rb532_gpio_get_int_status(unsigned gpio);
|
||||
|
||||
|
||||
/* Wrappers for the arch-neutral GPIO API */
|
||||
|
||||
static inline int gpio_request(unsigned gpio, const char *label)
|
||||
{
|
||||
/* Not yet implemented */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void gpio_free(unsigned gpio)
|
||||
{
|
||||
/* Not yet implemented */
|
||||
}
|
||||
|
||||
static inline int gpio_direction_input(unsigned gpio)
|
||||
{
|
||||
return rb532_gpio_direction_input(gpio);
|
||||
}
|
||||
|
||||
static inline int gpio_direction_output(unsigned gpio, int value)
|
||||
{
|
||||
return rb532_gpio_direction_output(gpio, value);
|
||||
}
|
||||
|
||||
static inline int gpio_get_value(unsigned gpio)
|
||||
{
|
||||
return rb532_gpio_get_value(gpio);
|
||||
}
|
||||
|
||||
static inline void gpio_set_value(unsigned gpio, int value)
|
||||
{
|
||||
rb532_gpio_set_value(gpio, value);
|
||||
}
|
||||
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
return gpio;
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned irq)
|
||||
{
|
||||
return irq;
|
||||
}
|
||||
|
||||
/* For cansleep */
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* _RC32434_GPIO_H_ */
|
||||
59
include/asm-mips/mach-rc32434/integ.h
Normal file
59
include/asm-mips/mach-rc32434/integ.h
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Definitions for the Watchdog registers
|
||||
*
|
||||
* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
|
||||
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __RC32434_INTEG_H__
|
||||
#define __RC32434_INTEG_H__
|
||||
|
||||
#include <asm/mach-rc32434/rb.h>
|
||||
|
||||
#define INTEG0_BASE_ADDR 0x18030030
|
||||
|
||||
struct integ {
|
||||
u32 errcs; /* sticky use ERRCS_ */
|
||||
u32 wtcount; /* Watchdog timer count reg. */
|
||||
u32 wtcompare; /* Watchdog timer timeout value. */
|
||||
u32 wtc; /* Watchdog timer control. use WTC_ */
|
||||
};
|
||||
|
||||
/* Error counters */
|
||||
#define RC32434_ERR_WTO 0
|
||||
#define RC32434_ERR_WNE 1
|
||||
#define RC32434_ERR_UCW 2
|
||||
#define RC32434_ERR_UCR 3
|
||||
#define RC32434_ERR_UPW 4
|
||||
#define RC32434_ERR_UPR 5
|
||||
#define RC32434_ERR_UDW 6
|
||||
#define RC32434_ERR_UDR 7
|
||||
#define RC32434_ERR_SAE 8
|
||||
#define RC32434_ERR_WRE 9
|
||||
|
||||
/* Watchdog control bits */
|
||||
#define RC32434_WTC_EN 0
|
||||
#define RC32434_WTC_TO 1
|
||||
|
||||
#endif /* __RC32434_INTEG_H__ */
|
||||
8
include/asm-mips/mach-rc32434/irq.h
Normal file
8
include/asm-mips/mach-rc32434/irq.h
Normal file
@ -0,0 +1,8 @@
|
||||
#ifndef __ASM_RC32434_IRQ_H
|
||||
#define __ASM_RC32434_IRQ_H
|
||||
|
||||
#define NR_IRQS 256
|
||||
|
||||
#include <asm/mach-generic/irq.h>
|
||||
|
||||
#endif /* __ASM_RC32434_IRQ_H */
|
||||
481
include/asm-mips/mach-rc32434/pci.h
Normal file
481
include/asm-mips/mach-rc32434/pci.h
Normal file
@ -0,0 +1,481 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
* Copyright 2004 IDT Inc. (rischelp@idt.com)
|
||||
*
|
||||
* Initial Release
|
||||
*/
|
||||
|
||||
#ifndef _ASM_RC32434_PCI_H_
|
||||
#define _ASM_RC32434_PCI_H_
|
||||
|
||||
#define epld_mask ((volatile unsigned char *)0xB900000d)
|
||||
|
||||
#define PCI0_BASE_ADDR 0x18080000
|
||||
#define PCI_LBA_COUNT 4
|
||||
|
||||
struct pci_map {
|
||||
u32 address; /* Address. */
|
||||
u32 control; /* Control. */
|
||||
u32 mapping; /* mapping. */
|
||||
};
|
||||
|
||||
struct pci_reg {
|
||||
u32 pcic;
|
||||
u32 pcis;
|
||||
u32 pcism;
|
||||
u32 pcicfga;
|
||||
u32 pcicfgd;
|
||||
volatile struct pci_map pcilba[PCI_LBA_COUNT];
|
||||
u32 pcidac;
|
||||
u32 pcidas;
|
||||
u32 pcidasm;
|
||||
u32 pcidad;
|
||||
u32 pcidma8c;
|
||||
u32 pcidma9c;
|
||||
u32 pcitc;
|
||||
};
|
||||
|
||||
#define PCI_MSU_COUNT 2
|
||||
|
||||
struct pci_msu {
|
||||
u32 pciim[PCI_MSU_COUNT];
|
||||
u32 pciom[PCI_MSU_COUNT];
|
||||
u32 pciid;
|
||||
u32 pciiic;
|
||||
u32 pciiim;
|
||||
u32 pciiod;
|
||||
u32 pciioic;
|
||||
u32 pciioim;
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI Control Register
|
||||
*/
|
||||
|
||||
#define PCI_CTL_EN (1 << 0)
|
||||
#define PCI_CTL_TNR (1 << 1)
|
||||
#define PCI_CTL_SCE (1 << 2)
|
||||
#define PCI_CTL_IEN (1 << 3)
|
||||
#define PCI_CTL_AAA (1 << 4)
|
||||
#define PCI_CTL_EAP (1 << 5)
|
||||
#define PCI_CTL_PCIM_BIT 6
|
||||
#define PCI_CTL_PCIM 0x000001c0
|
||||
|
||||
#define PCI_CTL_PCIM_DIS 0
|
||||
#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */
|
||||
#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */
|
||||
#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */
|
||||
#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */
|
||||
#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */
|
||||
#define PCI_CTL_PCIM_RSVD6 6
|
||||
#define PCI_CTL_PCIM_RSVD7 7
|
||||
|
||||
#define PCI_CTL_IGM (1 << 9)
|
||||
|
||||
/*
|
||||
* PCI Status Register
|
||||
*/
|
||||
|
||||
#define PCI_STAT_EED (1 << 0)
|
||||
#define PCI_STAT_WR (1 << 1)
|
||||
#define PCI_STAT_NMI (1 << 2)
|
||||
#define PCI_STAT_II (1 << 3)
|
||||
#define PCI_STAT_CWE (1 << 4)
|
||||
#define PCI_STAT_CRE (1 << 5)
|
||||
#define PCI_STAT_MDPE (1 << 6)
|
||||
#define PCI_STAT_STA (1 << 7)
|
||||
#define PCI_STAT_RTA (1 << 8)
|
||||
#define PCI_STAT_RMA (1 << 9)
|
||||
#define PCI_STAT_SSE (1 << 10)
|
||||
#define PCI_STAT_OSE (1 << 11)
|
||||
#define PCI_STAT_PE (1 << 12)
|
||||
#define PCI_STAT_TAE (1 << 13)
|
||||
#define PCI_STAT_RLE (1 << 14)
|
||||
#define PCI_STAT_BME (1 << 15)
|
||||
#define PCI_STAT_PRD (1 << 16)
|
||||
#define PCI_STAT_RIP (1 << 17)
|
||||
|
||||
/*
|
||||
* PCI Status Mask Register
|
||||
*/
|
||||
|
||||
#define PCI_STATM_EED PCI_STAT_EED
|
||||
#define PCI_STATM_WR PCI_STAT_WR
|
||||
#define PCI_STATM_NMI PCI_STAT_NMI
|
||||
#define PCI_STATM_II PCI_STAT_II
|
||||
#define PCI_STATM_CWE PCI_STAT_CWE
|
||||
#define PCI_STATM_CRE PCI_STAT_CRE
|
||||
#define PCI_STATM_MDPE PCI_STAT_MDPE
|
||||
#define PCI_STATM_STA PCI_STAT_STA
|
||||
#define PCI_STATM_RTA PCI_STAT_RTA
|
||||
#define PCI_STATM_RMA PCI_STAT_RMA
|
||||
#define PCI_STATM_SSE PCI_STAT_SSE
|
||||
#define PCI_STATM_OSE PCI_STAT_OSE
|
||||
#define PCI_STATM_PE PCI_STAT_PE
|
||||
#define PCI_STATM_TAE PCI_STAT_TAE
|
||||
#define PCI_STATM_RLE PCI_STAT_RLE
|
||||
#define PCI_STATM_BME PCI_STAT_BME
|
||||
#define PCI_STATM_PRD PCI_STAT_PRD
|
||||
#define PCI_STATM_RIP PCI_STAT_RIP
|
||||
|
||||
/*
|
||||
* PCI Configuration Address Register
|
||||
*/
|
||||
#define PCI_CFGA_REG_BIT 2
|
||||
#define PCI_CFGA_REG 0x000000fc
|
||||
#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */
|
||||
#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */
|
||||
#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */
|
||||
#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */
|
||||
#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */
|
||||
#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */
|
||||
#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */
|
||||
#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */
|
||||
#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */
|
||||
#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */
|
||||
#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */
|
||||
#define PCI_CFGA_REG_PBA0M (0x48 >> 2)
|
||||
#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */
|
||||
#define PCI_CFGA_REG_PBA1M (0x50 >> 2)
|
||||
#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */
|
||||
#define PCI_CFGA_REG_PBA2M (0x58 >> 2)
|
||||
#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */
|
||||
#define PCI_CFGA_REG_PBA3M (0x60 >> 2)
|
||||
#define PCI_CFGA_REG_PMGT (0x64 >> 2)
|
||||
#define PCI_CFGA_FUNC_BIT 8
|
||||
#define PCI_CFGA_FUNC 0x00000700
|
||||
#define PCI_CFGA_DEV_BIT 11
|
||||
#define PCI_CFGA_DEV 0x0000f800
|
||||
#define PCI_CFGA_DEV_INTERN 0
|
||||
#define PCI_CFGA_BUS_BIT 16
|
||||
#define PCI CFGA_BUS 0x00ff0000
|
||||
#define PCI_CFGA_BUS_TYPE0 0
|
||||
#define PCI_CFGA_EN (1 << 31)
|
||||
|
||||
/* PCI CFG04 commands */
|
||||
#define PCI_CFG04_CMD_IO_ENA (1 << 0)
|
||||
#define PCI_CFG04_CMD_MEM_ENA (1 << 1)
|
||||
#define PCI_CFG04_CMD_BM_ENA (1 << 2)
|
||||
#define PCI_CFG04_CMD_MW_INV (1 << 4)
|
||||
#define PCI_CFG04_CMD_PAR_ENA (1 << 6)
|
||||
#define PCI_CFG04_CMD_SER_ENA (1 << 8)
|
||||
#define PCI_CFG04_CMD_FAST_ENA (1 << 9)
|
||||
|
||||
/* PCI CFG04 status fields */
|
||||
#define PCI_CFG04_STAT_BIT 16
|
||||
#define PCI_CFG04_STAT 0xffff0000
|
||||
#define PCI_CFG04_STAT_66_MHZ (1 << 21)
|
||||
#define PCI_CFG04_STAT_FBB (1 << 23)
|
||||
#define PCI_CFG04_STAT_MDPE (1 << 24)
|
||||
#define PCI_CFG04_STAT_DST (1 << 25)
|
||||
#define PCI_CFG04_STAT_STA (1 << 27)
|
||||
#define PCI_CFG04_STAT_RTA (1 << 28)
|
||||
#define PCI_CFG04_STAT_RMA (1 << 29)
|
||||
#define PCI_CFG04_STAT_SSE (1 << 30)
|
||||
#define PCI_CFG04_STAT_PE (1 << 31)
|
||||
|
||||
#define PCI_PBA_MSI (1 << 0)
|
||||
#define PCI_PBA_P (1 << 2)
|
||||
|
||||
/* PCI PBAC registers */
|
||||
#define PCI_PBAC_MSI (1 << 0)
|
||||
#define PCI_PBAC_P (1 << 1)
|
||||
#define PCI_PBAC_SIZE_BIT 2
|
||||
#define PCI_PBAC_SIZE 0x0000007c
|
||||
#define PCI_PBAC_SB (1 << 7)
|
||||
#define PCI_PBAC_PP (1 << 8)
|
||||
#define PCI_PBAC_MR_BIT 9
|
||||
#define PCI_PBAC_MR 0x00000600
|
||||
#define PCI_PBAC_MR_RD 0
|
||||
#define PCI_PBAC_MR_RD_LINE 1
|
||||
#define PCI_PBAC_MR_RD_MULT 2
|
||||
#define PCI_PBAC_MRL (1 << 11)
|
||||
#define PCI_PBAC_MRM (1 << 12)
|
||||
#define PCI_PBAC_TRP (1 << 13)
|
||||
|
||||
#define PCI_CFG40_TRDY_TIM 0x000000ff
|
||||
#define PCI_CFG40_RET_LIM 0x0000ff00
|
||||
|
||||
/*
|
||||
* PCI Local Base Address [0|1|2|3] Register
|
||||
*/
|
||||
|
||||
#define PCI_LBA_BADDR_BIT 0
|
||||
#define PCI_LBA_BADDR 0xffffff00
|
||||
|
||||
/*
|
||||
* PCI Local Base Address Control Register
|
||||
*/
|
||||
|
||||
#define PCI_LBAC_MSI (1 << 0)
|
||||
#define PCI_LBAC_MSI_MEM 0
|
||||
#define PCI_LBAC_MSI_IO 1
|
||||
#define PCI_LBAC_SIZE_BIT 2
|
||||
#define PCI_LBAC_SIZE 0x0000007c
|
||||
#define PCI_LBAC_SB (1 << 7)
|
||||
#define PCI_LBAC_RT (1 << 8)
|
||||
#define PCI_LBAC_RT_NO_PREF 0
|
||||
#define PCI_LBAC_RT_PREF 1
|
||||
|
||||
/*
|
||||
* PCI Local Base Address [0|1|2|3] Mapping Register
|
||||
*/
|
||||
#define PCI_LBAM_MADDR_BIT 8
|
||||
#define PCI_LBAM_MADDR 0xffffff00
|
||||
|
||||
/*
|
||||
* PCI Decoupled Access Control Register
|
||||
*/
|
||||
#define PCI_DAC_DEN (1 << 0)
|
||||
|
||||
/*
|
||||
* PCI Decoupled Access Status Register
|
||||
*/
|
||||
#define PCI_DAS_D (1 << 0)
|
||||
#define PCI_DAS_B (1 << 1)
|
||||
#define PCI_DAS_E (1 << 2)
|
||||
#define PCI_DAS_OFE (1 << 3)
|
||||
#define PCI_DAS_OFF (1 << 4)
|
||||
#define PCI_DAS_IFE (1 << 5)
|
||||
#define PCI_DAS_IFF (1 << 6)
|
||||
|
||||
/*
|
||||
* PCI DMA Channel 8 Configuration Register
|
||||
*/
|
||||
#define PCI_DMA8C_MBS_BIT 0
|
||||
#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */
|
||||
#define PCI_DMA8C_OUR (1 << 12)
|
||||
|
||||
/*
|
||||
* PCI DMA Channel 9 Configuration Register
|
||||
*/
|
||||
#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */
|
||||
#define PCI_DMA9C_MBS 0x00000fff
|
||||
|
||||
/*
|
||||
* PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
|
||||
*/
|
||||
|
||||
#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */
|
||||
#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */
|
||||
/* These are for reads (DMA channel 8) */
|
||||
#define PCI_DMAD_DEVCMD_MR 0 /* memory read */
|
||||
#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */
|
||||
#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */
|
||||
#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */
|
||||
/* These are for writes (DMA channel 9) */
|
||||
#define PCI_DMAD_DEVCMD_MW 0 /* memory write */
|
||||
#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */
|
||||
#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */
|
||||
|
||||
/* Swap byte field applies to both DMA channel 8 and 9 */
|
||||
#define PCI_DMAD_SB (1 << 24) /* swap byte field */
|
||||
|
||||
|
||||
/*
|
||||
* PCI Target Control Register
|
||||
*/
|
||||
|
||||
#define PCI_TC_RTIMER_BIT 0
|
||||
#define PCI_TC_RTIMER 0x000000ff
|
||||
#define PCI_TC_DTIMER_BIT 8
|
||||
#define PCI_TC_DTIMER 0x0000ff00
|
||||
#define PCI_TC_RDR (1 << 18)
|
||||
#define PCI_TC_DDT (1 << 19)
|
||||
|
||||
/*
|
||||
* PCI messaging unit [applies to both inbound and outbound registers ]
|
||||
*/
|
||||
#define PCI_MSU_M0 (1 << 0)
|
||||
#define PCI_MSU_M1 (1 << 1)
|
||||
#define PCI_MSU_DB (1 << 2)
|
||||
|
||||
#define PCI_MSG_ADDR 0xB8088010
|
||||
#define PCI0_ADDR 0xB8080000
|
||||
#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
|
||||
#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
|
||||
|
||||
#define PCIM_SHFT 0x6
|
||||
#define PCIM_BIT_LEN 0x7
|
||||
#define PCIM_H_EA 0x3
|
||||
#define PCIM_H_IA_FIX 0x4
|
||||
#define PCIM_H_IA_RR 0x5
|
||||
#if 0
|
||||
#define PCI_ADDR_START 0x13000000
|
||||
#endif
|
||||
|
||||
#define PCI_ADDR_START 0x50000000
|
||||
|
||||
#define CPUTOPCI_MEM_WIN 0x02000000
|
||||
#define CPUTOPCI_IO_WIN 0x00100000
|
||||
#define PCILBA_SIZE_SHFT 2
|
||||
#define PCILBA_SIZE_MASK 0x1F
|
||||
#define SIZE_256MB 0x1C
|
||||
#define SIZE_128MB 0x1B
|
||||
#define SIZE_64MB 0x1A
|
||||
#define SIZE_32MB 0x19
|
||||
#define SIZE_16MB 0x18
|
||||
#define SIZE_4MB 0x16
|
||||
#define SIZE_2MB 0x15
|
||||
#define SIZE_1MB 0x14
|
||||
#define KORINA_CONFIG0_ADDR 0x80000000
|
||||
#define KORINA_CONFIG1_ADDR 0x80000004
|
||||
#define KORINA_CONFIG2_ADDR 0x80000008
|
||||
#define KORINA_CONFIG3_ADDR 0x8000000C
|
||||
#define KORINA_CONFIG4_ADDR 0x80000010
|
||||
#define KORINA_CONFIG5_ADDR 0x80000014
|
||||
#define KORINA_CONFIG6_ADDR 0x80000018
|
||||
#define KORINA_CONFIG7_ADDR 0x8000001C
|
||||
#define KORINA_CONFIG8_ADDR 0x80000020
|
||||
#define KORINA_CONFIG9_ADDR 0x80000024
|
||||
#define KORINA_CONFIG10_ADDR 0x80000028
|
||||
#define KORINA_CONFIG11_ADDR 0x8000002C
|
||||
#define KORINA_CONFIG12_ADDR 0x80000030
|
||||
#define KORINA_CONFIG13_ADDR 0x80000034
|
||||
#define KORINA_CONFIG14_ADDR 0x80000038
|
||||
#define KORINA_CONFIG15_ADDR 0x8000003C
|
||||
#define KORINA_CONFIG16_ADDR 0x80000040
|
||||
#define KORINA_CONFIG17_ADDR 0x80000044
|
||||
#define KORINA_CONFIG18_ADDR 0x80000048
|
||||
#define KORINA_CONFIG19_ADDR 0x8000004C
|
||||
#define KORINA_CONFIG20_ADDR 0x80000050
|
||||
#define KORINA_CONFIG21_ADDR 0x80000054
|
||||
#define KORINA_CONFIG22_ADDR 0x80000058
|
||||
#define KORINA_CONFIG23_ADDR 0x8000005C
|
||||
#define KORINA_CONFIG24_ADDR 0x80000060
|
||||
#define KORINA_CONFIG25_ADDR 0x80000064
|
||||
#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \
|
||||
PCI_CFG04_CMD_MEM_ENA | \
|
||||
PCI_CFG04_CMD_BM_ENA | \
|
||||
PCI_CFG04_CMD_MW_INV | \
|
||||
PCI_CFG04_CMD_PAR_ENA | \
|
||||
PCI_CFG04_CMD_SER_ENA)
|
||||
|
||||
#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \
|
||||
PCI_CFG04_STAT_STA | \
|
||||
PCI_CFG04_STAT_RTA | \
|
||||
PCI_CFG04_STAT_RMA | \
|
||||
PCI_CFG04_STAT_SSE | \
|
||||
PCI_CFG04_STAT_PE)
|
||||
|
||||
#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
|
||||
|
||||
#define KORINA_REVID 0
|
||||
#define KORINA_CLASS_CODE 0
|
||||
#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
|
||||
KORINA_REVID)
|
||||
|
||||
#define KORINA_CACHE_LINE_SIZE 4
|
||||
#define KORINA_MASTER_LAT 0x3c
|
||||
#define KORINA_HEADER_TYPE 0
|
||||
#define KORINA_BIST 0
|
||||
|
||||
#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
|
||||
(KORINA_HEADER_TYPE<<16) | \
|
||||
(KORINA_MASTER_LAT<<8) | \
|
||||
KORINA_CACHE_LINE_SIZE)
|
||||
|
||||
#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
|
||||
#define KORINA_BAR1 0x18800001 /* 1 MB IO */
|
||||
#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
|
||||
internal Registers */
|
||||
#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
|
||||
|
||||
#define KORINA_CNFG4 KORINA_BAR0
|
||||
#define KORINA_CNFG5 KORINA_BAR1
|
||||
#define KORINA_CNFG6 KORINA_BAR2
|
||||
#define KORINA_CNFG7 KORINA_BAR3
|
||||
|
||||
#define KORINA_SUBSYS_VENDOR_ID 0x011d
|
||||
#define KORINA_SUBSYSTEM_ID 0x0214
|
||||
#define KORINA_CNFG8 0
|
||||
#define KORINA_CNFG9 0
|
||||
#define KORINA_CNFG10 0
|
||||
#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
|
||||
KORINA_SUBSYSTEM_ID)
|
||||
#define KORINA_INT_LINE 1
|
||||
#define KORINA_INT_PIN 1
|
||||
#define KORINA_MIN_GNT 8
|
||||
#define KORINA_MAX_LAT 0x38
|
||||
#define KORINA_CNFG12 0
|
||||
#define KORINA_CNFG13 0
|
||||
#define KORINA_CNFG14 0
|
||||
#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
|
||||
(KORINA_MIN_GNT<<16) | \
|
||||
(KORINA_INT_PIN<<8) | \
|
||||
KORINA_INT_LINE)
|
||||
#define KORINA_RETRY_LIMIT 0x80
|
||||
#define KORINA_TRDY_LIMIT 0x80
|
||||
#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
|
||||
KORINA_TRDY_LIMIT)
|
||||
#define PCI_PBAxC_R 0x0
|
||||
#define PCI_PBAxC_RL 0x1
|
||||
#define PCI_PBAxC_RM 0x2
|
||||
#define SIZE_SHFT 2
|
||||
|
||||
#if defined(__MIPSEB__)
|
||||
#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \
|
||||
((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
|
||||
PCI_PBAC_PP | \
|
||||
(SIZE_128MB<<SIZE_SHFT) | \
|
||||
PCI_PBAC_P)
|
||||
#else
|
||||
#define KORINA_PBA0C (PCI_PBAC_MRL | \
|
||||
((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
|
||||
PCI_PBAC_PP | \
|
||||
(SIZE_128MB<<SIZE_SHFT) | \
|
||||
PCI_PBAC_P)
|
||||
#endif
|
||||
#define KORINA_CNFG17 KORINA_PBA0C
|
||||
#define KORINA_PBA0M 0x0
|
||||
#define KORINA_CNFG18 KORINA_PBA0M
|
||||
|
||||
#if defined(__MIPSEB__)
|
||||
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
|
||||
PCI_PBAC_MSI)
|
||||
#else
|
||||
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
|
||||
PCI_PBAC_MSI)
|
||||
#endif
|
||||
#define KORINA_CNFG19 KORINA_PBA1C
|
||||
#define KORINA_PBA1M 0x0
|
||||
#define KORINA_CNFG20 KORINA_PBA1M
|
||||
|
||||
#if defined(__MIPSEB__)
|
||||
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
|
||||
PCI_PBAC_MSI)
|
||||
#else
|
||||
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
|
||||
PCI_PBAC_MSI)
|
||||
#endif
|
||||
#define KORINA_CNFG21 KORINA_PBA2C
|
||||
#define KORINA_PBA2M 0x18000000
|
||||
#define KORINA_CNFG22 KORINA_PBA2M
|
||||
#define KORINA_PBA3C 0
|
||||
#define KORINA_CNFG23 KORINA_PBA3C
|
||||
#define KORINA_PBA3M 0
|
||||
#define KORINA_CNFG24 KORINA_PBA3M
|
||||
|
||||
#define PCITC_DTIMER_VAL 8
|
||||
#define PCITC_RTIMER_VAL 0x10
|
||||
|
||||
#endif /* __ASM_RC32434_PCI_H */
|
||||
44
include/asm-mips/mach-rc32434/prom.h
Normal file
44
include/asm-mips/mach-rc32434/prom.h
Normal file
@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Definitions for the PROM
|
||||
*
|
||||
* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
|
||||
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8))
|
||||
|
||||
#define GPIO_INIT_NOBUTTON ""
|
||||
#define GPIO_INIT_BUTTON " 2"
|
||||
|
||||
#define SR_NMI 0x00180000
|
||||
#define SERIAL_SPEED_ENTRY 0x00000001
|
||||
|
||||
#define FREQ_TAG "HZ="
|
||||
#define GPIO_TAG "gpio="
|
||||
#define KMAC_TAG "kmac="
|
||||
#define MEM_TAG "mem="
|
||||
#define BOARD_TAG "board="
|
||||
|
||||
#define BOARD_RB532 "500"
|
||||
#define BOARD_RB532A "500r5"
|
||||
81
include/asm-mips/mach-rc32434/rb.h
Normal file
81
include/asm-mips/mach-rc32434/rb.h
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Copyright (C) 2004 IDT Inc.
|
||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
||||
*/
|
||||
#ifndef __ASM_RC32434_RB_H
|
||||
#define __ASM_RC32434_RB_H
|
||||
|
||||
#include <linux/genhd.h>
|
||||
|
||||
#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
|
||||
#define DEV0BASE 0x010000
|
||||
#define DEV0MASK 0x010004
|
||||
#define DEV0C 0x010008
|
||||
#define DEV0T 0x01000C
|
||||
#define DEV1BASE 0x010010
|
||||
#define DEV1MASK 0x010014
|
||||
#define DEV1C 0x010018
|
||||
#define DEV1TC 0x01001C
|
||||
#define DEV2BASE 0x010020
|
||||
#define DEV2MASK 0x010024
|
||||
#define DEV2C 0x010028
|
||||
#define DEV2TC 0x01002C
|
||||
#define DEV3BASE 0x010030
|
||||
#define DEV3MASK 0x010034
|
||||
#define DEV3C 0x010038
|
||||
#define DEV3TC 0x01003C
|
||||
#define BTCS 0x010040
|
||||
#define BTCOMPARE 0x010044
|
||||
#define GPIOBASE 0x050000
|
||||
#define GPIOCFG 0x050004
|
||||
#define GPIOD 0x050008
|
||||
#define GPIOILEVEL 0x05000C
|
||||
#define GPIOISTAT 0x050010
|
||||
#define GPIONMIEN 0x050014
|
||||
#define IMASK6 0x038038
|
||||
#define LO_WPX (1 << 0)
|
||||
#define LO_ALE (1 << 1)
|
||||
#define LO_CLE (1 << 2)
|
||||
#define LO_CEX (1 << 3)
|
||||
#define LO_FOFF (1 << 5)
|
||||
#define LO_SPICS (1 << 6)
|
||||
#define LO_ULED (1 << 7)
|
||||
|
||||
#define BIT_TO_MASK(x) (1 << x)
|
||||
|
||||
struct dev_reg {
|
||||
u32 base;
|
||||
u32 mask;
|
||||
u32 ctl;
|
||||
u32 timing;
|
||||
};
|
||||
|
||||
struct korina_device {
|
||||
char *name;
|
||||
unsigned char mac[6];
|
||||
struct net_device *dev;
|
||||
};
|
||||
|
||||
struct cf_device {
|
||||
int gpio_pin;
|
||||
void *dev;
|
||||
struct gendisk *gd;
|
||||
};
|
||||
|
||||
struct mpmc_device {
|
||||
unsigned char state;
|
||||
spinlock_t lock;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
#endif /* __ASM_RC32434_RB_H */
|
||||
61
include/asm-mips/mach-rc32434/rc32434.h
Normal file
61
include/asm-mips/mach-rc32434/rc32434.h
Normal file
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Definitions for IDT RC323434 CPU.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_RC32434_RC32434_H_
|
||||
#define _ASM_RC32434_RC32434_H_
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define RC32434_REG_BASE 0x18000000
|
||||
#define RC32434_RST (1 << 15)
|
||||
|
||||
#define IDT_CLOCK_MULT 2
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
|
||||
/* Interrupt Controller */
|
||||
#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
|
||||
#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
|
||||
#define IC_GROUP_OFFSET 0x0C
|
||||
|
||||
#define NUM_INTR_GROUPS 5
|
||||
|
||||
/* 16550 UARTs */
|
||||
#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
|
||||
/* GRP3 IRQ numbers start here */
|
||||
#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
|
||||
/* GRP4 IRQ numbers start here */
|
||||
#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
|
||||
/* GRP5 IRQ numbers start here */
|
||||
#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
|
||||
#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
|
||||
|
||||
|
||||
#ifdef __MIPSEB__
|
||||
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
|
||||
#else
|
||||
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
|
||||
#endif
|
||||
|
||||
#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0)
|
||||
|
||||
/* cpu pipeline flush */
|
||||
static inline void rc32434_sync(void)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
static inline void rc32434_sync_udelay(int us)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
udelay(us);
|
||||
}
|
||||
|
||||
static inline void rc32434_sync_delay(int ms)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
mdelay(ms);
|
||||
}
|
||||
|
||||
#endif /* _ASM_RC32434_RC32434_H_ */
|
||||
65
include/asm-mips/mach-rc32434/timer.h
Normal file
65
include/asm-mips/mach-rc32434/timer.h
Normal file
@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Definitions for timer registers
|
||||
*
|
||||
* Copyright 2004 Philip Rischel <rischelp@idt.com>
|
||||
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_RC32434_TIMER_H
|
||||
#define __ASM_RC32434_TIMER_H
|
||||
|
||||
#include <asm/mach-rc32434/rb.h>
|
||||
|
||||
#define TIMER0_BASE_ADDR 0x18028000
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
struct timer_counter {
|
||||
u32 count;
|
||||
u32 compare;
|
||||
u32 ctc; /*use CTC_ */
|
||||
};
|
||||
|
||||
struct timer {
|
||||
struct timer_counter tim[TIMER_COUNT];
|
||||
u32 rcount; /* use RCOUNT_ */
|
||||
u32 rcompare; /* use RCOMPARE_ */
|
||||
u32 rtc; /* use RTC_ */
|
||||
};
|
||||
|
||||
#define RC32434_CTC_EN_BIT 0
|
||||
#define RC32434_CTC_TO_BIT 1
|
||||
|
||||
/* Real time clock registers */
|
||||
#define RC32434_RTC_MSK(x) BIT_TO_MASK(x)
|
||||
#define RC32434_RTC_CE_BIT 0
|
||||
#define RC32434_RTC_TO_BIT 1
|
||||
#define RC32434_RTC_RQE_BIT 2
|
||||
|
||||
/* Counter registers */
|
||||
#define RC32434_RCOUNT_BIT 0
|
||||
#define RC32434_RCOUNT_MSK 0x0000ffff
|
||||
#define RC32434_RCOMP_BIT 0
|
||||
#define RC32434_RCOMP_MSK 0x0000ffff
|
||||
|
||||
#endif /* __ASM_RC32434_TIMER_H */
|
||||
25
include/asm-mips/mach-rc32434/war.h
Normal file
25
include/asm-mips/mach-rc32434/war.h
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
|
||||
#define __ASM_MIPS_MACH_MIPS_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 1
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
|
||||
Loading…
Reference in New Issue
Block a user