forked from Minki/linux
staging: brcm80211: remove OSL_DELAY
and use udelay and mdelay instead Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
parent
5dc56c9f4c
commit
7383141b03
@ -198,7 +198,7 @@ u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, u32 addr, int *err)
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#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
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do {
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if (retry) /* wait for 1 ms till bus get settled down */
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OSL_DELAY(1000);
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udelay(1000);
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#endif
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status =
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sdioh_cfg_read(bcmsdh->sdioh, fnc_num, addr,
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@ -233,7 +233,7 @@ bcmsdh_cfg_write(void *sdh, uint fnc_num, u32 addr, u8 data, int *err)
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#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
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do {
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if (retry) /* wait for 1 ms till bus get settled down */
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OSL_DELAY(1000);
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udelay(1000);
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#endif
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status =
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sdioh_cfg_write(bcmsdh->sdioh, fnc_num, addr,
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@ -188,7 +188,7 @@ typedef struct dhd_pub {
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#define SPINWAIT_SLEEP(a, exp, us) do { \
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uint countdown = (us) + 9; \
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while ((exp) && (countdown >= 10)) { \
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OSL_DELAY(10); \
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udelay(10); \
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countdown -= 10; \
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} \
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} while (0)
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@ -132,7 +132,7 @@ void dhd_customer_gpio_wlan_ctrl(int onoff)
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bcm_wlan_power_on(1);
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#endif /* CUSTOMER_HW */
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/* Lets customer power to get stable */
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OSL_DELAY(200);
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udelay(200);
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break;
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}
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}
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@ -614,7 +614,7 @@ int dhd_timeout_expired(dhd_timeout_t *tmo)
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tmo->elapsed += tmo->increment;
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if (tmo->increment < tmo->tick) {
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OSL_DELAY(tmo->increment);
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udelay(tmo->increment);
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tmo->increment *= 2;
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if (tmo->increment > tmo->tick)
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tmo->increment = tmo->tick;
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@ -5271,7 +5271,7 @@ dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
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/* Now request ALP be put on the bus */
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bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
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DHD_INIT_CLKCTL2, &err);
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OSL_DELAY(65);
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udelay(65);
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for (fn = 0; fn <= numfn; fn++) {
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cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT);
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@ -42,7 +42,7 @@
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#define SPINWAIT(exp, us) { \
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uint countdown = (us) + 9; \
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while ((exp) && (countdown >= 10)) {\
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OSL_DELAY(10); \
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udelay(10); \
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countdown -= 10; \
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} \
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}
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@ -49,9 +49,6 @@ extern void osl_assert(char *exp, char *file, int line);
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#endif /* __GNUC__ */
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#endif /* defined(BCMDBG_ASSERT) */
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#define OSL_DELAY(usec) osl_delay(usec)
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extern void osl_delay(uint usec);
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/* PCI configuration space access macros */
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#define OSL_PCI_READ_CONFIG(osh, offset, size) \
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osl_pci_read_config((osh), (offset), (size))
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@ -201,7 +201,7 @@ void wlc_radioreg_enter(wlc_phy_t *pih)
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phy_info_t *pi = (phy_info_t *) pih;
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wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO);
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OSL_DELAY(10);
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udelay(10);
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}
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void wlc_radioreg_exit(wlc_phy_t *pih)
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@ -1316,20 +1316,20 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
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while ((i++ < count)
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&& (R_REG(pi->sh->osh, ®s->txe_status) & (1 << 7))) {
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OSL_DELAY(10);
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udelay(10);
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}
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i = 0;
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while ((i++ < 10)
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&& ((R_REG(pi->sh->osh, ®s->txe_status) & (1 << 10)) == 0)) {
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OSL_DELAY(10);
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udelay(10);
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}
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i = 0;
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while ((i++ < 10) && ((R_REG(pi->sh->osh, ®s->ifsstat) & (1 << 8)))) {
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OSL_DELAY(10);
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udelay(10);
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}
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if (!pa_on) {
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if (ISNPHY(pi))
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@ -1226,7 +1226,7 @@ void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec)
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if (!NORADIO_ENAB(pi->pubpi)) {
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wlc_lcnphy_radio_2064_channel_tune_4313(pi, channel);
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OSL_DELAY(1000);
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udelay(1000);
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}
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wlc_lcnphy_toggle_afe_pwdn(pi);
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@ -1832,7 +1832,7 @@ static bool wlc_lcnphy_iqcal_wait(phy_info_t *pi)
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uint delay_count = 0;
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while (wlc_lcnphy_iqcal_active(pi)) {
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OSL_DELAY(100);
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udelay(100);
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delay_count++;
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if (delay_count > (10 * 500))
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@ -1985,7 +1985,7 @@ wlc_lcnphy_tx_iqlo_cal(phy_info_t *pi,
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if (pi->phy_tx_tone_freq) {
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wlc_lcnphy_stop_tx_tone(pi);
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OSL_DELAY(5);
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udelay(5);
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wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
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} else {
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wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
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@ -2159,7 +2159,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
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s8 index;
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int i;
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phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
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OSL_DELAY(999);
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udelay(999);
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save_reg007 = (u8) read_radio_reg(pi, RADIO_2064_REG007);
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save_reg0FF = (u8) read_radio_reg(pi, RADIO_2064_REG0FF);
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@ -2269,7 +2269,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
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wlc_phy_do_dummy_tx(pi, true, OFF);
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if (!tempsense_done(pi))
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OSL_DELAY(10);
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udelay(10);
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write_radio_reg(pi, RADIO_2064_REG007, (u16) save_reg007);
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write_radio_reg(pi, RADIO_2064_REG0FF, (u16) save_reg0FF);
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@ -2284,7 +2284,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
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write_radio_reg(pi, 0x4a4, save_txpwrCtrlEn);
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if (!suspend)
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wlapi_enable_mac(pi->sh->physhim);
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OSL_DELAY(999);
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udelay(999);
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}
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void WLBANDINITFN(wlc_lcnphy_tx_pwr_ctrl_init) (wlc_phy_t *ppi)
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@ -3008,7 +3008,7 @@ s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode)
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mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
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OSL_DELAY(100);
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udelay(100);
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mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
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if (!suspend)
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@ -3069,7 +3069,7 @@ u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode)
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mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
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OSL_DELAY(100);
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udelay(100);
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mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
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if (!suspend)
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@ -3165,7 +3165,7 @@ wlc_lcnphy_rx_iq_est(phy_info_t *pi,
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result = false;
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goto cleanup;
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}
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OSL_DELAY(100);
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udelay(100);
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wait_count++;
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}
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@ -3392,7 +3392,7 @@ wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp,
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0, 0, 2, 2,
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(u16)
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tia_gain, 1, 0);
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OSL_DELAY(500);
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udelay(500);
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received_power =
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wlc_lcnphy_measure_digital_power(pi, 2000);
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@ -3740,7 +3740,7 @@ void WLBANDINITFN(wlc_phy_init_lcnphy) (phy_info_t *pi)
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mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
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OSL_DELAY(100);
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udelay(100);
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mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
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wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
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@ -3778,7 +3778,7 @@ wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, u16 *values_to_save)
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or_radio_reg(pi, RADIO_2064_REG036, 0x01);
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or_radio_reg(pi, RADIO_2064_REG11A, 0x18);
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OSL_DELAY(20);
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udelay(20);
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if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
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if (CHSPEC_IS5G(pi->radio_chanspec))
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@ -3792,7 +3792,7 @@ wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, u16 *values_to_save)
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or_radio_reg(pi, RADIO_2064_REG03A, 0x3);
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}
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OSL_DELAY(20);
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udelay(20);
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write_radio_reg(pi, RADIO_2064_REG025, 0xF);
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if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
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@ -3807,31 +3807,31 @@ wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, u16 *values_to_save)
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mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x6 << 1);
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}
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OSL_DELAY(20);
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udelay(20);
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write_radio_reg(pi, RADIO_2064_REG005, 0x8);
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or_radio_reg(pi, RADIO_2064_REG112, 0x80);
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OSL_DELAY(20);
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udelay(20);
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or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
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or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
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OSL_DELAY(20);
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udelay(20);
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or_radio_reg(pi, RADIO_2064_REG00B, 0x7);
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or_radio_reg(pi, RADIO_2064_REG113, 0x10);
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OSL_DELAY(20);
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udelay(20);
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write_radio_reg(pi, RADIO_2064_REG007, 0x1);
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OSL_DELAY(20);
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udelay(20);
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vmid = 0x2A6;
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mod_radio_reg(pi, RADIO_2064_REG0FC, 0x3 << 0, (vmid >> 8) & 0x3);
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write_radio_reg(pi, RADIO_2064_REG0FD, (vmid & 0xff));
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or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
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OSL_DELAY(20);
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udelay(20);
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or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
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OSL_DELAY(20);
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udelay(20);
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write_radio_reg(pi, RADIO_2064_REG012, 0x02);
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or_radio_reg(pi, RADIO_2064_REG112, 0x06);
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write_radio_reg(pi, RADIO_2064_REG036, 0x11);
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@ -3860,7 +3860,7 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
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W_REG(pi->sh->osh, &pi->regs->smpl_clct_strptr, 0x7E00);
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W_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr, 0x8000);
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OSL_DELAY(20);
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udelay(20);
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curval2 = R_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param);
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W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, curval2 | 0x30);
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@ -3882,7 +3882,7 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
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stpptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr);
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curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);
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do {
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OSL_DELAY(10);
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udelay(10);
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curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);
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timer++;
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} while ((curptr != stpptr) && (timer < 500));
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@ -4057,7 +4057,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
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or_phy_reg(pi, 0x6db, 0x3);
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wlc_lcnphy_tx_iqlo_loopback(pi, phy_c32);
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OSL_DELAY(500);
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udelay(500);
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phy_c28 = read_phy_reg(pi, 0x938);
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phy_c29 = read_phy_reg(pi, 0x4d7);
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phy_c30 = read_phy_reg(pi, 0x4d8);
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@ -4098,7 +4098,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
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phy_c16 = phy_c3.im - 256;
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}
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wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
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OSL_DELAY(20);
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udelay(20);
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for (phy_c8 = 0; phy_c7 != 0 && phy_c8 < num_levels; phy_c8++) {
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phy_c23 = 1;
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phy_c22 = 0;
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@ -4125,7 +4125,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
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while (1) {
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write_radio_reg(pi, RADIO_2064_REG026,
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(phy_c5 & 0x7) | ((phy_c5 & 0x7) << 4));
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OSL_DELAY(50);
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udelay(50);
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phy_c22 = 0;
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ptr[130] = 0;
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wlc_lcnphy_samp_cap(pi, 1, phy_c9, &ptr[0], 2);
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@ -4163,7 +4163,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
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phy_c12 = phy_c10;
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wlc_lcnphy_set_cc(pi, cal_type, phy_c11,
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phy_c12);
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OSL_DELAY(20);
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udelay(20);
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wlc_lcnphy_samp_cap(pi, 0, 0, ptr, 2);
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phy_c18 = 0;
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@ -4199,7 +4199,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
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phy_c16 = phy_c14;
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phy_c7 = phy_c7 >> 1;
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wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
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OSL_DELAY(20);
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udelay(20);
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}
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goto cleanup;
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cleanup:
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@ -4681,7 +4681,7 @@ static void wlc_lcnphy_rcal(phy_info_t *pi)
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or_radio_reg(pi, RADIO_2064_REG057, 0x01);
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or_radio_reg(pi, RADIO_2064_REG05B, 0x02);
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OSL_DELAY(5000);
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mdelay(5);
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SPINWAIT(!wlc_radio_2064_rcal_done(pi), 10 * 1000 * 1000);
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if (wlc_radio_2064_rcal_done(pi)) {
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@ -4846,11 +4846,11 @@ void wlc_2064_vco_cal(phy_info_t *pi)
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mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 1 << 3);
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calnrst = (u8) read_radio_reg(pi, RADIO_2064_REG056) & 0xf8;
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write_radio_reg(pi, RADIO_2064_REG056, calnrst);
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OSL_DELAY(1);
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udelay(1);
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write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x03);
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OSL_DELAY(1);
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udelay(1);
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write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x07);
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OSL_DELAY(300);
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udelay(300);
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mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 0);
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}
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@ -5008,7 +5008,7 @@ wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, u8 channel)
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write_radio_reg(pi, RADIO_2064_REG03D, 0x3);
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mod_radio_reg(pi, RADIO_2064_REG044, 0x0c, 0x0c);
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OSL_DELAY(1);
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udelay(1);
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wlc_2064_vco_cal(pi);
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@ -14967,7 +14967,7 @@ static void wlc_phy_resetcca_nphy(phy_info_t *pi)
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val = read_phy_reg(pi, 0x01);
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write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
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OSL_DELAY(1);
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udelay(1);
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write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
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wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
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||||
@ -17409,7 +17409,7 @@ static void wlc_phy_radio_postinit_2055(phy_info_t *pi)
|
||||
|
||||
or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_RST_N);
|
||||
|
||||
OSL_DELAY(1000);
|
||||
udelay(1000);
|
||||
|
||||
or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_START);
|
||||
|
||||
@ -17446,7 +17446,7 @@ static void wlc_phy_radio_postinit_2055(phy_info_t *pi)
|
||||
RADIO_2055_GAINBST_DISABLE);
|
||||
}
|
||||
|
||||
OSL_DELAY(2);
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
static void wlc_phy_radio_preinit_205x(phy_info_t *pi)
|
||||
@ -17530,7 +17530,7 @@ static void wlc_phy_radio_postinit_2056(phy_info_t *pi)
|
||||
|
||||
mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x2);
|
||||
mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x2);
|
||||
OSL_DELAY(1000);
|
||||
udelay(1000);
|
||||
mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x0);
|
||||
|
||||
if ((pi->sh->boardflags2 & BFL2_LEGACY)
|
||||
@ -17606,7 +17606,7 @@ static void wlc_phy_radio_postinit_2057(phy_info_t *pi)
|
||||
|
||||
mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x78);
|
||||
mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x80);
|
||||
OSL_DELAY(2000);
|
||||
mdelay(2);
|
||||
mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x0);
|
||||
mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x0);
|
||||
|
||||
@ -17868,7 +17868,7 @@ wlc_phy_chanspec_radio2055_setup(phy_info_t *pi, chan_info_nphy_2055_t *ci)
|
||||
write_radio_reg(pi, RADIO_2055_CORE2_TX_MX_BGTRIM,
|
||||
ci->RF_core2_tx_mx_bgtrim);
|
||||
|
||||
OSL_DELAY(50);
|
||||
udelay(50);
|
||||
|
||||
write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x05);
|
||||
write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x45);
|
||||
@ -17877,7 +17877,7 @@ wlc_phy_chanspec_radio2055_setup(phy_info_t *pi, chan_info_nphy_2055_t *ci)
|
||||
|
||||
write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x65);
|
||||
|
||||
OSL_DELAY(300);
|
||||
udelay(300);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -18217,7 +18217,7 @@ wlc_phy_chanspec_radio2056_setup(phy_info_t *pi,
|
||||
}
|
||||
}
|
||||
|
||||
OSL_DELAY(50);
|
||||
udelay(50);
|
||||
|
||||
wlc_phy_radio205x_vcocal_nphy(pi);
|
||||
}
|
||||
@ -18238,7 +18238,7 @@ void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi)
|
||||
write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x39);
|
||||
}
|
||||
|
||||
OSL_DELAY(300);
|
||||
udelay(300);
|
||||
}
|
||||
|
||||
#define MAX_205x_RCAL_WAITLOOPS 10000
|
||||
@ -18254,7 +18254,7 @@ static u16 wlc_phy_radio205x_rcal(phy_info_t *pi)
|
||||
|
||||
and_phy_reg(pi, 0x342, ~(0x1 << 1));
|
||||
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
|
||||
mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x1);
|
||||
mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
|
||||
@ -18262,7 +18262,7 @@ static u16 wlc_phy_radio205x_rcal(phy_info_t *pi)
|
||||
}
|
||||
mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x1);
|
||||
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
|
||||
mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x3, 0x3);
|
||||
|
||||
@ -18271,7 +18271,7 @@ static u16 wlc_phy_radio205x_rcal(phy_info_t *pi)
|
||||
if (rcal_reg & 0x1) {
|
||||
break;
|
||||
}
|
||||
OSL_DELAY(100);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
ASSERT(i < MAX_205x_RCAL_WAITLOOPS);
|
||||
@ -18304,11 +18304,11 @@ static u16 wlc_phy_radio205x_rcal(phy_info_t *pi)
|
||||
RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN);
|
||||
write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
|
||||
savereg | 0x7);
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
|
||||
write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
|
||||
0x1);
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
|
||||
write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
|
||||
0x9);
|
||||
@ -18320,7 +18320,7 @@ static u16 wlc_phy_radio205x_rcal(phy_info_t *pi)
|
||||
if (rcal_reg & 0x80) {
|
||||
break;
|
||||
}
|
||||
OSL_DELAY(100);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
ASSERT(i < MAX_205x_RCAL_WAITLOOPS);
|
||||
@ -18535,7 +18535,7 @@ wlc_phy_chanspec_radio2057_setup(phy_info_t *pi,
|
||||
}
|
||||
}
|
||||
|
||||
OSL_DELAY(50);
|
||||
udelay(50);
|
||||
|
||||
wlc_phy_radio205x_vcocal_nphy(pi);
|
||||
}
|
||||
@ -18567,7 +18567,7 @@ static u16 wlc_phy_radio2057_rccal(phy_info_t *pi)
|
||||
if (rccal_valid & 0x2) {
|
||||
break;
|
||||
}
|
||||
OSL_DELAY(500);
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
ASSERT(rccal_valid & 0x2);
|
||||
@ -18591,7 +18591,7 @@ static u16 wlc_phy_radio2057_rccal(phy_info_t *pi)
|
||||
if (rccal_valid & 0x2) {
|
||||
break;
|
||||
}
|
||||
OSL_DELAY(500);
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
ASSERT(rccal_valid & 0x2);
|
||||
@ -18616,7 +18616,7 @@ static u16 wlc_phy_radio2057_rccal(phy_info_t *pi)
|
||||
if (rccal_valid & 0x2) {
|
||||
break;
|
||||
}
|
||||
OSL_DELAY(500);
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
ASSERT(rccal_valid & 0x2);
|
||||
@ -20273,7 +20273,7 @@ wlc_phy_rfctrl_override_nphy(phy_info_t *pi, u16 field, u16 value,
|
||||
|
||||
or_phy_reg(pi, 0xec, (0x1 << 0));
|
||||
or_phy_reg(pi, 0x78, (0x1 << 0));
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
and_phy_reg(pi, 0xec, ~(0x1 << 0));
|
||||
}
|
||||
}
|
||||
@ -20801,7 +20801,7 @@ void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core_code, u8 rssi_type)
|
||||
mod_phy_reg(pi, 0xec, rfctrlovr_mask, rfctrlovr_val);
|
||||
|
||||
mod_phy_reg(pi, 0x78, (0x1 << 0), (startseq << 0));
|
||||
OSL_DELAY(20);
|
||||
udelay(20);
|
||||
|
||||
mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
|
||||
}
|
||||
@ -20983,7 +20983,7 @@ s16 wlc_phy_tempsense_nphy(phy_info_t *pi)
|
||||
mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
|
||||
mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
|
||||
mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
|
||||
OSL_DELAY(5);
|
||||
udelay(5);
|
||||
mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
|
||||
mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
|
||||
mod_phy_reg(pi, 0xa6, (0x1 << 3), 0);
|
||||
@ -21002,13 +21002,13 @@ s16 wlc_phy_tempsense_nphy(phy_info_t *pi)
|
||||
wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
|
||||
&auxADC_Av);
|
||||
|
||||
OSL_DELAY(3);
|
||||
udelay(3);
|
||||
|
||||
wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
|
||||
write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
|
||||
tempsense_Rcal | 0x03);
|
||||
|
||||
OSL_DELAY(5);
|
||||
udelay(5);
|
||||
wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
|
||||
|
||||
auxADC_Av = 0x7;
|
||||
@ -21031,13 +21031,13 @@ s16 wlc_phy_tempsense_nphy(phy_info_t *pi)
|
||||
wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
|
||||
&auxADC_Av);
|
||||
|
||||
OSL_DELAY(3);
|
||||
udelay(3);
|
||||
|
||||
wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
|
||||
write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
|
||||
tempsense_Rcal | 0x01);
|
||||
|
||||
OSL_DELAY(5);
|
||||
udelay(5);
|
||||
wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
|
||||
|
||||
write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
|
||||
@ -23714,7 +23714,7 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower, bool debug)
|
||||
wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &curr_m0m1);
|
||||
wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &curr_m0m1);
|
||||
|
||||
OSL_DELAY(50);
|
||||
udelay(50);
|
||||
|
||||
wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
|
||||
NPHY_CAL_TSSISAMPS);
|
||||
@ -23765,7 +23765,7 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower, bool debug)
|
||||
wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
|
||||
wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &dbg_m0m1);
|
||||
|
||||
OSL_DELAY(100);
|
||||
udelay(100);
|
||||
|
||||
wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
|
||||
NPHY_CAL_TSSISAMPS);
|
||||
@ -23773,7 +23773,7 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower, bool debug)
|
||||
wlc_phy_table_read_nphy(pi, 7, 1, (0x110 + core), 16,
|
||||
&radio_gain);
|
||||
|
||||
OSL_DELAY(4000000);
|
||||
mdelay(4000);
|
||||
pi->nphy_bb_mult_save = 0;
|
||||
wlc_phy_stopplayback_nphy(pi);
|
||||
}
|
||||
@ -25657,7 +25657,7 @@ wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
|
||||
|
||||
wlc_phy_tx_tone_nphy(pi, ref_tone, NPHY_RXCAL_TONEAMP,
|
||||
0, 1, false);
|
||||
OSL_DELAY(2);
|
||||
udelay(2);
|
||||
|
||||
wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
|
||||
|
||||
@ -25675,7 +25675,7 @@ wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
|
||||
|
||||
wlc_phy_tx_tone_nphy(pi, target_bw, NPHY_RXCAL_TONEAMP,
|
||||
0, 1, false);
|
||||
OSL_DELAY(2);
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
|
||||
@ -25761,7 +25761,7 @@ wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
|
||||
return best_rccal_val - 0x80;
|
||||
}
|
||||
|
||||
#define WAIT_FOR_SCOPE 4000000
|
||||
#define WAIT_FOR_SCOPE 4000
|
||||
static int
|
||||
wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t target_gain,
|
||||
u8 cal_type, bool debug)
|
||||
@ -25821,7 +25821,7 @@ wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t target_gain,
|
||||
false);
|
||||
|
||||
if (debug)
|
||||
OSL_DELAY(WAIT_FOR_SCOPE);
|
||||
mdelay(WAIT_FOR_SCOPE);
|
||||
|
||||
wlc_phy_calc_rx_iq_comp_nphy(pi, rx_core + 1);
|
||||
wlc_phy_stopplayback_nphy(pi);
|
||||
@ -26022,7 +26022,7 @@ wlc_phy_cal_rxiq_nphy_rev2(phy_info_t *pi, nphy_txgains_t target_gain,
|
||||
for (gain_pass = 0; gain_pass < 4; gain_pass++) {
|
||||
|
||||
if (debug)
|
||||
OSL_DELAY(WAIT_FOR_SCOPE);
|
||||
mdelay(WAIT_FOR_SCOPE);
|
||||
|
||||
if (gain_pass < 3) {
|
||||
curr_lna = lna_vals[gain_pass];
|
||||
@ -28219,7 +28219,7 @@ void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi)
|
||||
if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
|
||||
wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
|
||||
(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
|
||||
@ -28434,7 +28434,7 @@ static void wlc_phy_txpwrctrl_idle_tssi_nphy(phy_info_t *pi)
|
||||
|
||||
wlc_phy_tx_tone_nphy(pi, 4000, 0, 0, 0, false);
|
||||
|
||||
OSL_DELAY(20);
|
||||
udelay(20);
|
||||
int_val =
|
||||
wlc_phy_poll_rssi_nphy(pi, (u8) NPHY_RSSI_SEL_TSSI_2G, rssi_buf,
|
||||
1);
|
||||
@ -28490,7 +28490,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
|
||||
if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
|
||||
wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
|
||||
(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (pi->phyhang_avoid)
|
||||
@ -28647,7 +28647,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
|
||||
if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
|
||||
wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
|
||||
(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (NREV_GE(pi->pubpi.phy_rev, 7)) {
|
||||
|
@ -939,7 +939,7 @@ wlc_ampdu_dotxstatus(ampdu_info_t *ampdu, struct scb *scb, void *p,
|
||||
while (((s1 =
|
||||
R_REG(wlc->osh,
|
||||
&wlc->regs->frmtxstatus)) & TXS_V) == 0) {
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
status_delay++;
|
||||
if (status_delay > 10) {
|
||||
ASSERT(status_delay <= 10);
|
||||
|
@ -1324,10 +1324,10 @@ int wlc_bmac_down_finish(wlc_hw_info_t *wlc_hw)
|
||||
void wlc_bmac_wait_for_wake(wlc_hw_info_t *wlc_hw)
|
||||
{
|
||||
if (D11REV_IS(wlc_hw->corerev, 4)) /* no slowclock */
|
||||
OSL_DELAY(5);
|
||||
udelay(5);
|
||||
else {
|
||||
/* delay before first read of ucode state */
|
||||
OSL_DELAY(40);
|
||||
udelay(40);
|
||||
|
||||
/* wait until ucode is no longer asleep */
|
||||
SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
|
||||
@ -1373,7 +1373,7 @@ static void wlc_clkctl_clk(wlc_hw_info_t *wlc_hw, uint mode)
|
||||
OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
|
||||
CCS_FORCEHT);
|
||||
|
||||
OSL_DELAY(64);
|
||||
udelay(64);
|
||||
|
||||
SPINWAIT(((R_REG
|
||||
(wlc_hw->osh,
|
||||
@ -1980,16 +1980,16 @@ void wlc_bmac_core_phy_clk(wlc_hw_info_t *wlc_hw, bool clk)
|
||||
|
||||
si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
|
||||
(SICF_PRST | SICF_FGC));
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
|
||||
} else { /* take phy out of reset */
|
||||
|
||||
si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
|
||||
}
|
||||
}
|
||||
@ -2001,16 +2001,16 @@ void wlc_bmac_core_phypll_reset(wlc_hw_info_t *wlc_hw)
|
||||
|
||||
si_corereg(wlc_hw->sih, SI_CC_IDX,
|
||||
offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
si_corereg(wlc_hw->sih, SI_CC_IDX,
|
||||
offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
si_corereg(wlc_hw->sih, SI_CC_IDX,
|
||||
offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
si_corereg(wlc_hw->sih, SI_CC_IDX,
|
||||
offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* light way to turn on phy clock without reset for NPHY only
|
||||
@ -2056,7 +2056,7 @@ void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
|
||||
/* Set the PHY bandwidth */
|
||||
si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
|
||||
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
|
||||
/* Perform a soft reset of the PHY PLL */
|
||||
wlc_bmac_core_phypll_reset(wlc_hw);
|
||||
@ -2072,7 +2072,7 @@ void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
|
||||
(SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
|
||||
}
|
||||
|
||||
OSL_DELAY(2);
|
||||
udelay(2);
|
||||
wlc_bmac_core_phy_clk(wlc_hw, ON);
|
||||
|
||||
if (pih)
|
||||
@ -2311,7 +2311,7 @@ static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo)
|
||||
|
||||
if (!rxidle && (rcv_frm_cnt != 0))
|
||||
WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw->unit, __func__, fifo, rcv_frm_cnt));
|
||||
OSL_DELAY(2000);
|
||||
mdelay(2);
|
||||
}
|
||||
|
||||
return dma_rxreset(di);
|
||||
@ -3004,7 +3004,7 @@ u32 wlc_intrsoff(wlc_info_t *wlc)
|
||||
|
||||
W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
|
||||
(void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask); /* sync readback */
|
||||
OSL_DELAY(1); /* ensure int line is no longer driven */
|
||||
udelay(1); /* ensure int line is no longer driven */
|
||||
wlc->macintmask = 0;
|
||||
|
||||
/* return previous macintmask; resolve race between us and our isr */
|
||||
|
@ -591,10 +591,10 @@ void ai_core_disable(si_t *sih, u32 bits)
|
||||
|
||||
W_REG(sii->osh, &ai->ioctrl, bits);
|
||||
dummy = R_REG(sii->osh, &ai->ioctrl);
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
|
||||
W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* reset and re-enable a core
|
||||
@ -623,11 +623,11 @@ void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
|
||||
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
|
||||
dummy = R_REG(sii->osh, &ai->ioctrl);
|
||||
W_REG(sii->osh, &ai->resetctrl, 0);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
|
||||
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
|
||||
dummy = R_REG(sii->osh, &ai->ioctrl);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
|
||||
|
@ -695,7 +695,7 @@ static void *hndotp_init(si_t *sih)
|
||||
(clkdiv & ~CLKD_OTP) | (otpdiv << CLKD_OTP_SHIFT);
|
||||
W_REG(osh, &cc->clkdiv, clkdiv);
|
||||
}
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
|
||||
ret = (void *)oi;
|
||||
}
|
||||
|
@ -1004,7 +1004,7 @@ static void *BCMFASTPATH _dma_rx(dma_info_t *di)
|
||||
#if defined(__mips__)
|
||||
if (!len) {
|
||||
while (!(len = *(u16 *) OSL_UNCACHED(PKTDATA(head))))
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
|
||||
*(u16 *) PKTDATA(head) = htol16((u16) len);
|
||||
}
|
||||
@ -1599,7 +1599,7 @@ static bool dma32_txreset(dma_info_t *di)
|
||||
XS_XS_DISABLED), 10000);
|
||||
|
||||
/* wait for the last transaction to complete */
|
||||
OSL_DELAY(300);
|
||||
udelay(300);
|
||||
|
||||
return status == XS_XS_DISABLED;
|
||||
}
|
||||
@ -1649,7 +1649,7 @@ static bool dma32_txsuspendedidle(dma_info_t *di)
|
||||
if ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
|
||||
return 0;
|
||||
|
||||
OSL_DELAY(2);
|
||||
udelay(2);
|
||||
return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) ==
|
||||
XS_XS_IDLE);
|
||||
}
|
||||
@ -2162,7 +2162,7 @@ static bool dma64_txreset(dma_info_t *di)
|
||||
!= D64_XS0_XS_DISABLED), 10000);
|
||||
|
||||
/* wait for the last transaction to complete */
|
||||
OSL_DELAY(300);
|
||||
udelay(300);
|
||||
|
||||
return status == D64_XS0_XS_DISABLED;
|
||||
}
|
||||
|
@ -863,7 +863,7 @@ void si_pmu_res_init(si_t *sih, osl_t *osh)
|
||||
}
|
||||
|
||||
/* Add some delay; allow resources to come up and settle. */
|
||||
OSL_DELAY(2000);
|
||||
mdelay(2);
|
||||
|
||||
/* Return to original core */
|
||||
si_setcoreidx(sih, origidx);
|
||||
@ -1295,13 +1295,13 @@ static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
|
||||
AND_REG(osh, &cc->max_res_mask,
|
||||
~(PMURES_BIT(RES4319_HT_AVAIL)));
|
||||
|
||||
OSL_DELAY(100);
|
||||
udelay(100);
|
||||
AND_REG(osh, &cc->min_res_mask,
|
||||
~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
|
||||
AND_REG(osh, &cc->max_res_mask,
|
||||
~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
|
||||
|
||||
OSL_DELAY(100);
|
||||
udelay(100);
|
||||
SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
|
||||
PMU_MAX_TRANSITION_DLY);
|
||||
ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
|
||||
@ -1317,7 +1317,7 @@ static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
|
||||
AND_REG(osh, &cc->max_res_mask,
|
||||
~(PMURES_BIT(RES4336_HT_AVAIL) |
|
||||
PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
|
||||
OSL_DELAY(100);
|
||||
udelay(100);
|
||||
SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
|
||||
PMU_MAX_TRANSITION_DLY);
|
||||
ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
|
||||
@ -1330,7 +1330,7 @@ static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
|
||||
AND_REG(osh, &cc->max_res_mask,
|
||||
~(PMURES_BIT(RES4330_HT_AVAIL) |
|
||||
PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
|
||||
OSL_DELAY(100);
|
||||
udelay(100);
|
||||
SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
|
||||
PMU_MAX_TRANSITION_DLY);
|
||||
ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
|
||||
@ -1854,7 +1854,7 @@ u32 si_pmu_ilp_clock(si_t *sih, osl_t *osh)
|
||||
chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
|
||||
ASSERT(cc != NULL);
|
||||
start = R_REG(osh, &cc->pmutimer);
|
||||
OSL_DELAY(ILP_CALC_DUR * 1000);
|
||||
mdelay(ILP_CALC_DUR);
|
||||
end = R_REG(osh, &cc->pmutimer);
|
||||
delta = end - start;
|
||||
ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
|
||||
@ -2642,7 +2642,7 @@ u32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh)
|
||||
1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
|
||||
|
||||
/* Delay for well over 4 ILP clocks */
|
||||
OSL_DELAY(1000);
|
||||
udelay(1000);
|
||||
|
||||
/* Read the latched number of ALP ticks per 4 ILP ticks */
|
||||
ilp_ctr =
|
||||
|
@ -591,17 +591,6 @@ void osl_assert(char *exp, char *file, int line)
|
||||
}
|
||||
#endif /* defined(BCMDBG_ASSERT) */
|
||||
|
||||
void osl_delay(uint usec)
|
||||
{
|
||||
uint d;
|
||||
|
||||
while (usec > 0) {
|
||||
d = min(usec, (uint)1000);
|
||||
udelay(d);
|
||||
usec -= d;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(BCMSDIO) && !defined(BRCM_FULLMAC)
|
||||
u8 osl_readb(osl_t *osh, volatile u8 *r)
|
||||
{
|
||||
|
@ -103,7 +103,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi);
|
||||
} while (0)
|
||||
|
||||
/* delay needed between the mdio control/ mdiodata register data access */
|
||||
#define PR28829_DELAY() OSL_DELAY(10)
|
||||
#define PR28829_DELAY() udelay(10)
|
||||
|
||||
/* Initialize the PCI core. It's caller's responsibility to make sure that this is done
|
||||
* only once
|
||||
@ -281,7 +281,7 @@ static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
|
||||
MDIOCTL_ACCESS_DONE) {
|
||||
break;
|
||||
}
|
||||
OSL_DELAY(1000);
|
||||
udelay(1000);
|
||||
i++;
|
||||
}
|
||||
|
||||
@ -342,7 +342,7 @@ pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
|
||||
W_REG(pi->osh, (&pcieregs->mdiocontrol), 0);
|
||||
return 0;
|
||||
}
|
||||
OSL_DELAY(1000);
|
||||
udelay(1000);
|
||||
i++;
|
||||
}
|
||||
|
||||
|
@ -477,7 +477,7 @@ void sb_core_disable(si_t *sih, u32 bits)
|
||||
(preserve core-specific bits) */
|
||||
OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
|
||||
dummy = R_SBREG(sii, &sb->sbtmstatelow);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
|
||||
if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
|
||||
SI_ERROR(("%s: target state still busy\n", __func__));
|
||||
@ -485,7 +485,7 @@ void sb_core_disable(si_t *sih, u32 bits)
|
||||
if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
|
||||
OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
|
||||
dummy = R_SBREG(sii, &sb->sbimstate);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
|
||||
}
|
||||
|
||||
@ -494,7 +494,7 @@ void sb_core_disable(si_t *sih, u32 bits)
|
||||
(((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
|
||||
SBTML_REJ | SBTML_RESET));
|
||||
dummy = R_SBREG(sii, &sb->sbtmstatelow);
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
|
||||
/* don't forget to clear the initiator reject bit */
|
||||
if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
|
||||
@ -504,7 +504,7 @@ disable:
|
||||
/* leave reset and reject asserted */
|
||||
W_SBREG(sii, &sb->sbtmstatelow,
|
||||
((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* reset and re-enable a core
|
||||
@ -538,7 +538,7 @@ void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
|
||||
(((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
|
||||
SBTML_SICF_SHIFT) | SBTML_RESET));
|
||||
dummy = R_SBREG(sii, &sb->sbtmstatelow);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
|
||||
if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR)
|
||||
W_SBREG(sii, &sb->sbtmstatehigh, 0);
|
||||
@ -552,13 +552,13 @@ void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
|
||||
((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
|
||||
SBTML_SICF_SHIFT));
|
||||
dummy = R_SBREG(sii, &sb->sbtmstatelow);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
|
||||
/* leave clock enabled */
|
||||
W_SBREG(sii, &sb->sbtmstatelow,
|
||||
((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
|
||||
dummy = R_SBREG(sii, &sb->sbtmstatelow);
|
||||
OSL_DELAY(1);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
u32 sb_base(u32 admatch)
|
||||
|
@ -152,7 +152,7 @@ static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
|
||||
bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
|
||||
SBSDIO_FUNC1_CHIPCLKCSR,
|
||||
clkset, &err);
|
||||
OSL_DELAY(65);
|
||||
udelay(65);
|
||||
}
|
||||
}
|
||||
|
||||
@ -607,7 +607,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh,
|
||||
W_REG(osh, &cc->clkdiv, clkdiv);
|
||||
SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
|
||||
}
|
||||
OSL_DELAY(10);
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/* Init nvram from flash if it exists */
|
||||
@ -1308,7 +1308,7 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
|
||||
sizeof(u32), out);
|
||||
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
|
||||
sizeof(u32), outen);
|
||||
OSL_DELAY(XTAL_ON_DELAY);
|
||||
udelay(XTAL_ON_DELAY);
|
||||
}
|
||||
|
||||
/* turn pll on */
|
||||
@ -1316,7 +1316,7 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
|
||||
out &= ~PCI_CFG_GPIO_PLL;
|
||||
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
|
||||
sizeof(u32), out);
|
||||
OSL_DELAY(2000);
|
||||
mdelay(2);
|
||||
}
|
||||
} else {
|
||||
if (what & XTAL)
|
||||
@ -1416,7 +1416,7 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
|
||||
== 0), PMU_MAX_TRANSITION_DLY);
|
||||
ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
|
||||
} else {
|
||||
OSL_DELAY(PLL_DELAY);
|
||||
udelay(PLL_DELAY);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -2018,6 +2018,6 @@ void si_otp_power(si_t *sih, bool on)
|
||||
{
|
||||
if (PMUCTL_ENAB(sih))
|
||||
si_pmu_otp_power(sih, si_osh(sih), on);
|
||||
OSL_DELAY(1000);
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user