phy: for 5.5
*) Add a new PHY driver for USB3 PHY on Allwinner H6 SoC
*) Add a new PHY driver for Innosilicon Video Combo PHY(MIPI/LVDS/TTL)
*) Add support in xusb-tegra210 PHY driver to get USB device mode functional
in Tegra 210
*) Add support for SM8150 QMP UFS PHY in phy-qcom-qmp PHY driver
*) Fix smatch warning (array off by one) in phy-rcar-gen2 PHY driver
*) Enable mac tx internal delay for rgmii-rxid in phy-gmii-sel driver
*) Fix phy-qcom-usb-hs from registering multiple extcon notifiers during PHY
power cycle
*) Use devm_platform_ioremap_resource() in phy-mvebu-a3700-utmi,
phy-hisi-inno-usb2, phy-histb-combphy and regulator_bulk_set_supply_names()
in xusb to simplify code
*) Remove unused variable in xusb-tegra210 and phy-dm816x-usb
*) Fix sparse warnings in phy-brcm-usb-init
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Merge tag 'phy-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next
Kishon writes:
phy: for 5.5
*) Add a new PHY driver for USB3 PHY on Allwinner H6 SoC
*) Add a new PHY driver for Innosilicon Video Combo PHY(MIPI/LVDS/TTL)
*) Add support in xusb-tegra210 PHY driver to get USB device mode functional
in Tegra 210
*) Add support for SM8150 QMP UFS PHY in phy-qcom-qmp PHY driver
*) Fix smatch warning (array off by one) in phy-rcar-gen2 PHY driver
*) Enable mac tx internal delay for rgmii-rxid in phy-gmii-sel driver
*) Fix phy-qcom-usb-hs from registering multiple extcon notifiers during PHY
power cycle
*) Use devm_platform_ioremap_resource() in phy-mvebu-a3700-utmi,
phy-hisi-inno-usb2, phy-histb-combphy and regulator_bulk_set_supply_names()
in xusb to simplify code
*) Remove unused variable in xusb-tegra210 and phy-dm816x-usb
*) Fix sparse warnings in phy-brcm-usb-init
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* tag 'phy-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (28 commits)
phy: phy-rockchip-inno-usb2: add phy description for px30
phy: qcom-usb-hs: Fix extcon double register after power cycle
phy: renesas: phy-rcar-gen2: Fix the array off by one warning
phy: lantiq: vrx200-pcie: fix error return code in ltq_vrx200_pcie_phy_power_on()
dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy
phy/rockchip: Add support for Innosilicon MIPI/LVDS/TTL PHY
phy: add PHY_MODE_LVDS
phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
dt-bindings: Add bindings for USB3 phy on Allwinner H6
phy: qcom-qmp: Add SM8150 QMP UFS PHY support
dt-bindings: phy-qcom-qmp: Add sm8150 UFS phy compatible string
phy: ti: gmii-sel: fix mac tx internal delay for rgmii-rxid
phy: tegra: use regulator_bulk_set_supply_names()
phy: ti: dm816x: remove set but not used variable 'phy_data'
phy: renesas: rcar-gen3-usb2: Fix sysfs interface of "role"
phy: tegra: xusb: Add vbus override support on Tegra186
phy: tegra: xusb: Add vbus override support on Tegra210
phy: tegra: xusb: Add usb3 port fake support on Tegra210
phy: tegra: xusb: Add XUSB dual mode support on Tegra210
dt-bindings: rcar-gen3-phy-usb3: Add r8a774b1 support
...
This commit is contained in:
Greg Kroah-Hartman
commit
7383092c4d
@ -0,0 +1,47 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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||||
# Copyright 2019 Ondrej Jirman <megous@megous.com>
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%YAML 1.2
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---
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||||
$id: "http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#"
|
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
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|
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title: Allwinner H6 USB3 PHY
|
||||
|
||||
maintainers:
|
||||
- Ondrej Jirman <megous@megous.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun50i-h6-usb3-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- resets
|
||||
- "#phy-cells"
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||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun50i-h6-ccu.h>
|
||||
#include <dt-bindings/reset/sun50i-h6-ccu.h>
|
||||
phy@5210000 {
|
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compatible = "allwinner,sun50i-h6-usb3-phy";
|
||||
reg = <0x5210000 0x10000>;
|
||||
clocks = <&ccu CLK_USB_PHY1>;
|
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resets = <&ccu RST_USB_PHY1>;
|
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#phy-cells = <0>;
|
||||
};
|
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@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
|
||||
|
||||
Required properties (phy (parent) node):
|
||||
- compatible : should be one of the listed compatibles:
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||||
* "rockchip,px30-usb2phy"
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* "rockchip,rk3228-usb2phy"
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* "rockchip,rk3328-usb2phy"
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* "rockchip,rk3366-usb2phy"
|
||||
|
||||
@ -14,7 +14,8 @@ Required properties:
|
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"qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
|
||||
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
|
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"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
|
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"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
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"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
|
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"qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150.
|
||||
|
||||
- reg:
|
||||
- index 0: address and length of register set for PHY's common
|
||||
@ -57,6 +58,8 @@ Required properties:
|
||||
"aux", "cfg_ahb", "ref", "com_aux".
|
||||
For "qcom,sdm845-qmp-ufs-phy" must contain:
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||||
"ref", "ref_aux".
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For "qcom,sm8150-qmp-ufs-phy" must contain:
|
||||
"ref", "ref_aux".
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||||
|
||||
- resets: a list of phandles and reset controller specifier pairs,
|
||||
one for each entry in reset-names.
|
||||
@ -83,6 +86,8 @@ Required properties:
|
||||
"phy", "common".
|
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For "qcom,sdm845-qmp-ufs-phy": must contain:
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"ufsphy".
|
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For "qcom,sm8150-qmp-ufs-phy": must contain:
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"ufsphy".
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- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
|
||||
|
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@ -10,6 +10,8 @@ Required properties:
|
||||
SoC.
|
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"renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
|
||||
SoC.
|
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"renesas,usb2-phy-r8a774b1" if the device is a part of an R8A774B1
|
||||
SoC.
|
||||
"renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0
|
||||
SoC.
|
||||
"renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
|
||||
|
||||
@ -8,6 +8,8 @@ need this driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: "renesas,r8a774a1-usb3-phy" if the device is a part of an R8A774A1
|
||||
SoC.
|
||||
"renesas,r8a774b1-usb3-phy" if the device is a part of an R8A774B1
|
||||
SoC.
|
||||
"renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
|
||||
SoC.
|
||||
|
||||
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip MIPI DPHY with additional LVDS/TTL modes
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,px30-dsi-dphy
|
||||
- rockchip,rk3128-dsi-dphy
|
||||
- rockchip,rk3368-dsi-dphy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PLL reference clock
|
||||
- description: Module clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
- const: pclk
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: phandle to the associated power domain
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: exclusive PHY reset line
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: apb
|
||||
|
||||
required:
|
||||
- "#phy-cells"
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dsi_dphy: phy@ff2e0000 {
|
||||
compatible = "rockchip,px30-video-phy";
|
||||
reg = <0x0 0xff2e0000 0x0 0x10000>;
|
||||
clocks = <&pmucru 13>, <&cru 12>;
|
||||
clock-names = "ref", "pclk";
|
||||
#clock-cells = <0>;
|
||||
resets = <&cru 12>;
|
||||
reset-names = "apb";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -45,3 +45,14 @@ config PHY_SUN9I_USB
|
||||
sun9i SoCs.
|
||||
|
||||
This driver controls each individual USB 2 host PHY.
|
||||
|
||||
config PHY_SUN50I_USB3
|
||||
tristate "Allwinner H6 SoC USB3 PHY driver"
|
||||
depends on ARCH_SUNXI && HAS_IOMEM && OF
|
||||
depends on RESET_CONTROLLER
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Enable this to support the USB3.0-capable transceiver that is
|
||||
part of Allwinner H6 SoC.
|
||||
|
||||
This driver controls each individual USB 2+3 host PHY combo.
|
||||
|
||||
@ -2,3 +2,4 @@
|
||||
obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
|
||||
obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY) += phy-sun6i-mipi-dphy.o
|
||||
obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o
|
||||
obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o
|
||||
|
||||
190
drivers/phy/allwinner/phy-sun50i-usb3.c
Normal file
190
drivers/phy/allwinner/phy-sun50i-usb3.c
Normal file
@ -0,0 +1,190 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Allwinner sun50i(H6) USB 3.0 phy driver
|
||||
*
|
||||
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
* Based on phy-sun9i-usb.c, which is:
|
||||
*
|
||||
* Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* Based on code from Allwinner BSP, which is:
|
||||
*
|
||||
* Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
/* Interface Status and Control Registers */
|
||||
#define SUNXI_ISCR 0x00
|
||||
#define SUNXI_PIPE_CLOCK_CONTROL 0x14
|
||||
#define SUNXI_PHY_TUNE_LOW 0x18
|
||||
#define SUNXI_PHY_TUNE_HIGH 0x1c
|
||||
#define SUNXI_PHY_EXTERNAL_CONTROL 0x20
|
||||
|
||||
/* USB2.0 Interface Status and Control Register */
|
||||
#define SUNXI_ISCR_FORCE_VBUS (3 << 12)
|
||||
|
||||
/* PIPE Clock Control Register */
|
||||
#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6)
|
||||
|
||||
/* PHY External Control Register */
|
||||
#define SUNXI_PEC_EXTERN_VBUS (3 << 1)
|
||||
#define SUNXI_PEC_SSC_EN (1 << 24)
|
||||
#define SUNXI_PEC_REF_SSP_EN (1 << 26)
|
||||
|
||||
/* PHY Tune High Register */
|
||||
#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19)
|
||||
#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)
|
||||
#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13)
|
||||
#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)
|
||||
#define SUNXI_TX_SWING_FULL(n) ((n) << 6)
|
||||
#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)
|
||||
#define SUNXI_LOS_BIAS(n) ((n) << 3)
|
||||
#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
|
||||
#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
|
||||
#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2)
|
||||
|
||||
struct sun50i_usb3_phy {
|
||||
struct phy *phy;
|
||||
void __iomem *regs;
|
||||
struct reset_control *reset;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
|
||||
val |= SUNXI_PEC_EXTERN_VBUS;
|
||||
val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
|
||||
writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
|
||||
|
||||
val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
|
||||
val |= SUNXI_PCC_PIPE_CLK_OPEN;
|
||||
writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
|
||||
|
||||
val = readl(phy->regs + SUNXI_ISCR);
|
||||
val |= SUNXI_ISCR_FORCE_VBUS;
|
||||
writel(val, phy->regs + SUNXI_ISCR);
|
||||
|
||||
/*
|
||||
* All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
|
||||
* registers are directly taken from the BSP USB3 driver from
|
||||
* Allwiner.
|
||||
*/
|
||||
writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
|
||||
|
||||
val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
|
||||
val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
|
||||
SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
|
||||
SUNXI_TX_DEEMPH_3P5DB_MASK);
|
||||
val |= SUNXI_TXVBOOSTLVL(0x7);
|
||||
val |= SUNXI_LOS_BIAS(0x7);
|
||||
val |= SUNXI_TX_SWING_FULL(0x55);
|
||||
val |= SUNXI_TX_DEEMPH_6DB(0x20);
|
||||
val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
|
||||
writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
|
||||
}
|
||||
|
||||
static int sun50i_usb3_phy_init(struct phy *_phy)
|
||||
{
|
||||
struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(phy->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_control_deassert(phy->reset);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(phy->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
sun50i_usb3_phy_open(phy);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun50i_usb3_phy_exit(struct phy *_phy)
|
||||
{
|
||||
struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
|
||||
|
||||
reset_control_assert(phy->reset);
|
||||
clk_disable_unprepare(phy->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops sun50i_usb3_phy_ops = {
|
||||
.init = sun50i_usb3_phy_init,
|
||||
.exit = sun50i_usb3_phy_exit,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int sun50i_usb3_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sun50i_usb3_phy *phy;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_provider *phy_provider;
|
||||
struct resource *res;
|
||||
|
||||
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
phy->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(phy->clk)) {
|
||||
if (PTR_ERR(phy->clk) != -EPROBE_DEFER)
|
||||
dev_err(dev, "failed to get phy clock\n");
|
||||
return PTR_ERR(phy->clk);
|
||||
}
|
||||
|
||||
phy->reset = devm_reset_control_get(dev, NULL);
|
||||
if (IS_ERR(phy->reset)) {
|
||||
dev_err(dev, "failed to get reset control\n");
|
||||
return PTR_ERR(phy->reset);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
phy->regs = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(phy->regs))
|
||||
return PTR_ERR(phy->regs);
|
||||
|
||||
phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
|
||||
if (IS_ERR(phy->phy)) {
|
||||
dev_err(dev, "failed to create PHY\n");
|
||||
return PTR_ERR(phy->phy);
|
||||
}
|
||||
|
||||
phy_set_drvdata(phy->phy, phy);
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
|
||||
return PTR_ERR_OR_ZERO(phy_provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id sun50i_usb3_phy_of_match[] = {
|
||||
{ .compatible = "allwinner,sun50i-h6-usb3-phy" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
|
||||
|
||||
static struct platform_driver sun50i_usb3_phy_driver = {
|
||||
.probe = sun50i_usb3_phy_probe,
|
||||
.driver = {
|
||||
.of_match_table = sun50i_usb3_phy_of_match,
|
||||
.name = "sun50i-usb3-phy",
|
||||
}
|
||||
};
|
||||
module_platform_driver(sun50i_usb3_phy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Allwinner H6 USB 3.0 phy driver");
|
||||
MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -126,8 +126,8 @@ enum {
|
||||
USB_CTRL_SELECTOR_COUNT,
|
||||
};
|
||||
|
||||
#define USB_CTRL_REG(base, reg) ((void *)base + USB_CTRL_##reg)
|
||||
#define USB_XHCI_EC_REG(base, reg) ((void *)base + USB_XHCI_EC_##reg)
|
||||
#define USB_CTRL_REG(base, reg) ((void __iomem *)base + USB_CTRL_##reg)
|
||||
#define USB_XHCI_EC_REG(base, reg) ((void __iomem *)base + USB_XHCI_EC_##reg)
|
||||
#define USB_CTRL_MASK(reg, field) \
|
||||
USB_CTRL_##reg##_##field##_MASK
|
||||
#define USB_CTRL_MASK_FAMILY(params, reg, field) \
|
||||
@ -416,7 +416,7 @@ void usb_ctrl_unset_family(struct brcm_usb_init_params *params,
|
||||
u32 reg_offset, u32 field)
|
||||
{
|
||||
u32 mask;
|
||||
void *reg;
|
||||
void __iomem *reg;
|
||||
|
||||
mask = params->usb_reg_bits_map[field];
|
||||
reg = params->ctrl_regs + reg_offset;
|
||||
@ -428,7 +428,7 @@ void usb_ctrl_set_family(struct brcm_usb_init_params *params,
|
||||
u32 reg_offset, u32 field)
|
||||
{
|
||||
u32 mask;
|
||||
void *reg;
|
||||
void __iomem *reg;
|
||||
|
||||
mask = params->usb_reg_bits_map[field];
|
||||
reg = params->ctrl_regs + reg_offset;
|
||||
@ -707,7 +707,7 @@ static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params)
|
||||
void __iomem *xhci_ec_base = params->xhci_ec_regs;
|
||||
u32 val;
|
||||
|
||||
if (params->family_id != 0x74371000 || xhci_ec_base == 0)
|
||||
if (params->family_id != 0x74371000 || !xhci_ec_base)
|
||||
return;
|
||||
brcmusb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR));
|
||||
val = brcmusb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
|
||||
|
||||
@ -114,7 +114,6 @@ static int hisi_inno_phy_probe(struct platform_device *pdev)
|
||||
struct hisi_inno_phy_priv *priv;
|
||||
struct phy_provider *provider;
|
||||
struct device_node *child;
|
||||
struct resource *res;
|
||||
int i = 0;
|
||||
int ret;
|
||||
|
||||
@ -122,8 +121,7 @@ static int hisi_inno_phy_probe(struct platform_device *pdev)
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->mmio = devm_ioremap_resource(dev, res);
|
||||
priv->mmio = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(priv->mmio)) {
|
||||
ret = PTR_ERR(priv->mmio);
|
||||
return ret;
|
||||
|
||||
@ -195,7 +195,6 @@ static int histb_combphy_probe(struct platform_device *pdev)
|
||||
struct histb_combphy_priv *priv;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct histb_combphy_mode *mode;
|
||||
struct resource *res;
|
||||
u32 vals[3];
|
||||
int ret;
|
||||
|
||||
@ -203,8 +202,7 @@ static int histb_combphy_probe(struct platform_device *pdev)
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->mmio = devm_ioremap_resource(dev, res);
|
||||
priv->mmio = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(priv->mmio)) {
|
||||
ret = PTR_ERR(priv->mmio);
|
||||
return ret;
|
||||
|
||||
@ -323,7 +323,8 @@ static int ltq_vrx200_pcie_phy_power_on(struct phy *phy)
|
||||
goto err_disable_pdi_clk;
|
||||
|
||||
/* Check if we are in "startup ready" status */
|
||||
if (ltq_vrx200_pcie_phy_wait_for_pll(phy) != 0)
|
||||
ret = ltq_vrx200_pcie_phy_wait_for_pll(phy);
|
||||
if (ret)
|
||||
goto err_disable_phy_clk;
|
||||
|
||||
ltq_vrx200_pcie_phy_apply_workarounds(phy);
|
||||
|
||||
@ -216,20 +216,13 @@ static int mvebu_a3700_utmi_phy_probe(struct platform_device *pdev)
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mvebu_a3700_utmi *utmi;
|
||||
struct phy_provider *provider;
|
||||
struct resource *res;
|
||||
|
||||
utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL);
|
||||
if (!utmi)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Get UTMI memory region */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "Missing UTMI PHY memory resource\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
utmi->regs = devm_ioremap_resource(dev, res);
|
||||
utmi->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(utmi->regs))
|
||||
return PTR_ERR(utmi->regs);
|
||||
|
||||
|
||||
@ -1342,7 +1342,7 @@ static int xgene_phy_hw_initialize(struct xgene_phy_ctx *ctx,
|
||||
static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane)
|
||||
{
|
||||
int i;
|
||||
struct {
|
||||
static const struct {
|
||||
u32 reg;
|
||||
u32 val;
|
||||
} serdes_reg[] = {
|
||||
|
||||
@ -165,6 +165,11 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
|
||||
[QPHY_PCS_READY_STATUS] = 0x160,
|
||||
};
|
||||
|
||||
static const unsigned int sm8150_ufsphy_regs_layout[] = {
|
||||
[QPHY_START_CTRL] = 0x00,
|
||||
[QPHY_PCS_READY_STATUS] = 0x180,
|
||||
};
|
||||
|
||||
static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
|
||||
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
|
||||
@ -879,6 +884,93 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
|
||||
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
|
||||
};
|
||||
|
||||
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
|
||||
QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
|
||||
|
||||
/* Rate B */
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
|
||||
};
|
||||
|
||||
static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
|
||||
};
|
||||
|
||||
static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
|
||||
|
||||
};
|
||||
|
||||
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
|
||||
QMP_PHY_INIT_CFG(QPHY_V4_RX_SIGDET_CTRL2, 0x6d),
|
||||
QMP_PHY_INIT_CFG(QPHY_V4_TX_LARGE_AMP_DRV_LVL, 0x0a),
|
||||
QMP_PHY_INIT_CFG(QPHY_V4_TX_SMALL_AMP_DRV_LVL, 0x02),
|
||||
QMP_PHY_INIT_CFG(QPHY_V4_TX_MID_TERM_CTRL1, 0x43),
|
||||
QMP_PHY_INIT_CFG(QPHY_V4_DEBUG_BUS_CLKSEL, 0x1f),
|
||||
QMP_PHY_INIT_CFG(QPHY_V4_RX_MIN_HIBERN8_TIME, 0xff),
|
||||
QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02),
|
||||
};
|
||||
|
||||
/* struct qmp_phy_cfg - per-PHY initialization config */
|
||||
struct qmp_phy_cfg {
|
||||
@ -1276,6 +1368,31 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
|
||||
.is_dual_lane_phy = true,
|
||||
};
|
||||
|
||||
static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
|
||||
.type = PHY_TYPE_UFS,
|
||||
.nlanes = 2,
|
||||
|
||||
.serdes_tbl = sm8150_ufsphy_serdes_tbl,
|
||||
.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
|
||||
.tx_tbl = sm8150_ufsphy_tx_tbl,
|
||||
.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
|
||||
.rx_tbl = sm8150_ufsphy_rx_tbl,
|
||||
.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
|
||||
.pcs_tbl = sm8150_ufsphy_pcs_tbl,
|
||||
.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
|
||||
.clk_list = sdm845_ufs_phy_clk_l,
|
||||
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
|
||||
.vreg_list = qmp_phy_vreg_l,
|
||||
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
||||
.regs = sm8150_ufsphy_regs_layout,
|
||||
|
||||
.start_ctrl = SERDES_START,
|
||||
.pwrdn_ctrl = SW_PWRDN,
|
||||
|
||||
.is_dual_lane_phy = true,
|
||||
.no_pcs_sw_reset = true,
|
||||
};
|
||||
|
||||
static void qcom_qmp_phy_configure(void __iomem *base,
|
||||
const unsigned int *regs,
|
||||
const struct qmp_phy_init_tbl tbl[],
|
||||
@ -1998,6 +2115,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
|
||||
}, {
|
||||
.compatible = "qcom,msm8998-qmp-usb3-phy",
|
||||
.data = &msm8998_usb3phy_cfg,
|
||||
}, {
|
||||
.compatible = "qcom,sm8150-qmp-ufs-phy",
|
||||
.data = &sm8150_ufsphy_cfg,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
@ -313,4 +313,100 @@
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
|
||||
|
||||
/* Only for QMP V4 PHY - QSERDES COM registers */
|
||||
#define QSERDES_V4_COM_PLL_IVCO 0x058
|
||||
#define QSERDES_V4_COM_CMN_IPTRIM 0x060
|
||||
#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
|
||||
#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
|
||||
#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
|
||||
#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
|
||||
#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
|
||||
#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
|
||||
#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
|
||||
#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
|
||||
#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
|
||||
#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
|
||||
#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
|
||||
#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
|
||||
#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
|
||||
#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
|
||||
#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
|
||||
#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
|
||||
#define QSERDES_V4_COM_HSCLK_SEL 0x158
|
||||
#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
|
||||
|
||||
/* Only for QMP V4 PHY - TX registers */
|
||||
#define QSERDES_V4_TX_LANE_MODE_1 0x84
|
||||
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
|
||||
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
|
||||
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0
|
||||
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4
|
||||
#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
|
||||
|
||||
/* Only for QMP V4 PHY - RX registers */
|
||||
#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
|
||||
#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
|
||||
#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
|
||||
#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
|
||||
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
|
||||
#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
|
||||
#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
|
||||
#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
|
||||
#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
|
||||
#define QSERDES_V4_RX_RX_TERM_BW 0x080
|
||||
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
|
||||
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
|
||||
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
|
||||
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
|
||||
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
|
||||
#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
|
||||
#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
|
||||
#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
|
||||
#define QSERDES_V4_RX_SIGDET_LVL 0x120
|
||||
#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
|
||||
#define QSERDES_V4_RX_RX_BAND 0x128
|
||||
#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
|
||||
#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
|
||||
#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
|
||||
#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
|
||||
|
||||
/* Only for QMP V4 PHY - PCS registers */
|
||||
#define QPHY_V4_PHY_START 0x000
|
||||
#define QPHY_V4_POWER_DOWN_CONTROL 0x004
|
||||
#define QPHY_V4_SW_RESET 0x008
|
||||
#define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB 0x00c
|
||||
#define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB 0x010
|
||||
#define QPHY_V4_PLL_CNTL 0x02c
|
||||
#define QPHY_V4_TX_LARGE_AMP_DRV_LVL 0x030
|
||||
#define QPHY_V4_TX_SMALL_AMP_DRV_LVL 0x038
|
||||
#define QPHY_V4_BIST_FIXED_PAT_CTRL 0x060
|
||||
#define QPHY_V4_TX_HSGEAR_CAPABILITY 0x074
|
||||
#define QPHY_V4_RX_HSGEAR_CAPABILITY 0x0b4
|
||||
#define QPHY_V4_DEBUG_BUS_CLKSEL 0x124
|
||||
#define QPHY_V4_LINECFG_DISABLE 0x148
|
||||
#define QPHY_V4_RX_MIN_HIBERN8_TIME 0x150
|
||||
#define QPHY_V4_RX_SIGDET_CTRL2 0x158
|
||||
#define QPHY_V4_TX_PWM_GEAR_BAND 0x160
|
||||
#define QPHY_V4_TX_HS_GEAR_BAND 0x168
|
||||
#define QPHY_V4_PCS_READY_STATUS 0x180
|
||||
#define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8
|
||||
#define QPHY_V4_MULTI_LANE_CTRL1 0x1e0
|
||||
|
||||
#endif
|
||||
|
||||
@ -158,8 +158,8 @@ static int qcom_usb_hs_phy_power_on(struct phy *phy)
|
||||
/* setup initial state */
|
||||
qcom_usb_hs_phy_vbus_notifier(&uphy->vbus_notify, state,
|
||||
uphy->vbus_edev);
|
||||
ret = devm_extcon_register_notifier(&ulpi->dev, uphy->vbus_edev,
|
||||
EXTCON_USB, &uphy->vbus_notify);
|
||||
ret = extcon_register_notifier(uphy->vbus_edev, EXTCON_USB,
|
||||
&uphy->vbus_notify);
|
||||
if (ret)
|
||||
goto err_ulpi;
|
||||
}
|
||||
@ -180,6 +180,9 @@ static int qcom_usb_hs_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct qcom_usb_hs_phy *uphy = phy_get_drvdata(phy);
|
||||
|
||||
if (uphy->vbus_edev)
|
||||
extcon_unregister_notifier(uphy->vbus_edev, EXTCON_USB,
|
||||
&uphy->vbus_notify);
|
||||
regulator_disable(uphy->v3p3);
|
||||
regulator_disable(uphy->v1p8);
|
||||
clk_disable_unprepare(uphy->sleep_clk);
|
||||
|
||||
@ -71,6 +71,7 @@ struct rcar_gen2_phy_driver {
|
||||
struct rcar_gen2_phy_data {
|
||||
const struct phy_ops *gen2_phy_ops;
|
||||
const u32 (*select_value)[PHYS_PER_CHANNEL];
|
||||
const u32 num_channels;
|
||||
};
|
||||
|
||||
static int rcar_gen2_phy_init(struct phy *p)
|
||||
@ -271,11 +272,13 @@ static const u32 usb20_select_value[][PHYS_PER_CHANNEL] = {
|
||||
static const struct rcar_gen2_phy_data rcar_gen2_usb_phy_data = {
|
||||
.gen2_phy_ops = &rcar_gen2_phy_ops,
|
||||
.select_value = pci_select_value,
|
||||
.num_channels = ARRAY_SIZE(pci_select_value),
|
||||
};
|
||||
|
||||
static const struct rcar_gen2_phy_data rz_g1c_usb_phy_data = {
|
||||
.gen2_phy_ops = &rz_g1c_phy_ops,
|
||||
.select_value = usb20_select_value,
|
||||
.num_channels = ARRAY_SIZE(usb20_select_value),
|
||||
};
|
||||
|
||||
static const struct of_device_id rcar_gen2_phy_match_table[] = {
|
||||
@ -389,7 +392,7 @@ static int rcar_gen2_phy_probe(struct platform_device *pdev)
|
||||
channel->selected_phy = -1;
|
||||
|
||||
error = of_property_read_u32(np, "reg", &channel_num);
|
||||
if (error || channel_num > 2) {
|
||||
if (error || channel_num >= data->num_channels) {
|
||||
dev_err(dev, "Invalid \"reg\" property\n");
|
||||
of_node_put(np);
|
||||
return error;
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/usb/of.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
@ -320,9 +321,9 @@ static ssize_t role_store(struct device *dev, struct device_attribute *attr,
|
||||
if (!ch->is_otg_channel || !rcar_gen3_is_any_rphy_initialized(ch))
|
||||
return -EIO;
|
||||
|
||||
if (!strncmp(buf, "host", strlen("host")))
|
||||
if (sysfs_streq(buf, "host"))
|
||||
new_mode = PHY_MODE_USB_HOST;
|
||||
else if (!strncmp(buf, "peripheral", strlen("peripheral")))
|
||||
else if (sysfs_streq(buf, "peripheral"))
|
||||
new_mode = PHY_MODE_USB_DEVICE;
|
||||
else
|
||||
return -EINVAL;
|
||||
@ -614,7 +615,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(channel->base);
|
||||
|
||||
/* call request_irq for OTG */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
irq = platform_get_irq_optional(pdev, 0);
|
||||
if (irq >= 0) {
|
||||
INIT_WORK(&channel->work, rcar_gen3_phy_usb2_work);
|
||||
irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
|
||||
|
||||
@ -35,6 +35,14 @@ config PHY_ROCKCHIP_INNO_USB2
|
||||
help
|
||||
Support for Rockchip USB2.0 PHY with Innosilicon IP block.
|
||||
|
||||
config PHY_ROCKCHIP_INNO_DSIDPHY
|
||||
tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
|
||||
depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
|
||||
Innosilicon IP block.
|
||||
|
||||
config PHY_ROCKCHIP_PCIE
|
||||
tristate "Rockchip PCIe PHY Driver"
|
||||
depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
|
||||
805
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
Normal file
805
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
Normal file
@ -0,0 +1,805 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
|
||||
*
|
||||
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
|
||||
#define PSEC_PER_SEC 1000000000000LL
|
||||
|
||||
#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
|
||||
|
||||
/*
|
||||
* The offset address[7:0] is distributed two parts, one from the bit7 to bit5
|
||||
* is the first address, the other from the bit4 to bit0 is the second address.
|
||||
* when you configure the registers, you must set both of them. The Clock Lane
|
||||
* and Data Lane use the same registers with the same second address, but the
|
||||
* first address is different.
|
||||
*/
|
||||
#define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
|
||||
#define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
|
||||
#define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
|
||||
SECOND_ADDRESS(second))
|
||||
|
||||
/* Analog Register Part: reg00 */
|
||||
#define BANDGAP_POWER_MASK BIT(7)
|
||||
#define BANDGAP_POWER_DOWN BIT(7)
|
||||
#define BANDGAP_POWER_ON 0
|
||||
#define LANE_EN_MASK GENMASK(6, 2)
|
||||
#define LANE_EN_CK BIT(6)
|
||||
#define LANE_EN_3 BIT(5)
|
||||
#define LANE_EN_2 BIT(4)
|
||||
#define LANE_EN_1 BIT(3)
|
||||
#define LANE_EN_0 BIT(2)
|
||||
#define POWER_WORK_MASK GENMASK(1, 0)
|
||||
#define POWER_WORK_ENABLE UPDATE(1, 1, 0)
|
||||
#define POWER_WORK_DISABLE UPDATE(2, 1, 0)
|
||||
/* Analog Register Part: reg01 */
|
||||
#define REG_SYNCRST_MASK BIT(2)
|
||||
#define REG_SYNCRST_RESET BIT(2)
|
||||
#define REG_SYNCRST_NORMAL 0
|
||||
#define REG_LDOPD_MASK BIT(1)
|
||||
#define REG_LDOPD_POWER_DOWN BIT(1)
|
||||
#define REG_LDOPD_POWER_ON 0
|
||||
#define REG_PLLPD_MASK BIT(0)
|
||||
#define REG_PLLPD_POWER_DOWN BIT(0)
|
||||
#define REG_PLLPD_POWER_ON 0
|
||||
/* Analog Register Part: reg03 */
|
||||
#define REG_FBDIV_HI_MASK BIT(5)
|
||||
#define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5)
|
||||
#define REG_PREDIV_MASK GENMASK(4, 0)
|
||||
#define REG_PREDIV(x) UPDATE(x, 4, 0)
|
||||
/* Analog Register Part: reg04 */
|
||||
#define REG_FBDIV_LO_MASK GENMASK(7, 0)
|
||||
#define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
|
||||
/* Analog Register Part: reg05 */
|
||||
#define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
|
||||
#define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
|
||||
#define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
|
||||
#define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
|
||||
/* Analog Register Part: reg06 */
|
||||
#define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
|
||||
#define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
|
||||
#define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
|
||||
#define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
|
||||
/* Analog Register Part: reg07 */
|
||||
#define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
|
||||
#define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
|
||||
#define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
|
||||
#define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
|
||||
/* Analog Register Part: reg08 */
|
||||
#define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
|
||||
#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
|
||||
#define SAMPLE_CLOCK_DIRECTION_FORWARD 0
|
||||
/* Digital Register Part: reg00 */
|
||||
#define REG_DIG_RSTN_MASK BIT(0)
|
||||
#define REG_DIG_RSTN_NORMAL BIT(0)
|
||||
#define REG_DIG_RSTN_RESET 0
|
||||
/* Digital Register Part: reg01 */
|
||||
#define INVERT_TXCLKESC_MASK BIT(1)
|
||||
#define INVERT_TXCLKESC_ENABLE BIT(1)
|
||||
#define INVERT_TXCLKESC_DISABLE 0
|
||||
#define INVERT_TXBYTECLKHS_MASK BIT(0)
|
||||
#define INVERT_TXBYTECLKHS_ENABLE BIT(0)
|
||||
#define INVERT_TXBYTECLKHS_DISABLE 0
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
|
||||
#define T_LPX_CNT_MASK GENMASK(5, 0)
|
||||
#define T_LPX_CNT(x) UPDATE(x, 5, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
|
||||
#define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
|
||||
#define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
|
||||
#define T_HS_ZERO_CNT_MASK GENMASK(5, 0)
|
||||
#define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
|
||||
#define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
|
||||
#define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
|
||||
#define T_HS_EXIT_CNT_MASK GENMASK(4, 0)
|
||||
#define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
|
||||
#define T_CLK_POST_CNT_MASK GENMASK(3, 0)
|
||||
#define T_CLK_POST_CNT(x) UPDATE(x, 3, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
|
||||
#define LPDT_TX_PPI_SYNC_MASK BIT(2)
|
||||
#define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
|
||||
#define LPDT_TX_PPI_SYNC_DISABLE 0
|
||||
#define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
|
||||
#define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
|
||||
#define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
|
||||
#define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
|
||||
#define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
|
||||
#define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
|
||||
#define T_TA_GO_CNT_MASK GENMASK(5, 0)
|
||||
#define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
|
||||
#define T_TA_SURE_CNT_MASK GENMASK(5, 0)
|
||||
#define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
|
||||
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
|
||||
#define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
|
||||
#define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
|
||||
/* LVDS Register Part: reg00 */
|
||||
#define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
|
||||
#define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
|
||||
#define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
|
||||
/* LVDS Register Part: reg01 */
|
||||
#define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
|
||||
#define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
|
||||
#define LVDS_DIGITAL_INTERNAL_DISABLE 0
|
||||
/* LVDS Register Part: reg03 */
|
||||
#define MODE_ENABLE_MASK GENMASK(2, 0)
|
||||
#define TTL_MODE_ENABLE BIT(2)
|
||||
#define LVDS_MODE_ENABLE BIT(1)
|
||||
#define MIPI_MODE_ENABLE BIT(0)
|
||||
/* LVDS Register Part: reg0b */
|
||||
#define LVDS_LANE_EN_MASK GENMASK(7, 3)
|
||||
#define LVDS_DATA_LANE0_EN BIT(7)
|
||||
#define LVDS_DATA_LANE1_EN BIT(6)
|
||||
#define LVDS_DATA_LANE2_EN BIT(5)
|
||||
#define LVDS_DATA_LANE3_EN BIT(4)
|
||||
#define LVDS_CLK_LANE_EN BIT(3)
|
||||
#define LVDS_PLL_POWER_MASK BIT(2)
|
||||
#define LVDS_PLL_POWER_OFF BIT(2)
|
||||
#define LVDS_PLL_POWER_ON 0
|
||||
#define LVDS_BANDGAP_POWER_MASK BIT(0)
|
||||
#define LVDS_BANDGAP_POWER_DOWN BIT(0)
|
||||
#define LVDS_BANDGAP_POWER_ON 0
|
||||
|
||||
#define DSI_PHY_RSTZ 0xa0
|
||||
#define PHY_ENABLECLK BIT(2)
|
||||
#define DSI_PHY_STATUS 0xb0
|
||||
#define PHY_LOCK BIT(0)
|
||||
|
||||
struct mipi_dphy_timing {
|
||||
unsigned int clkmiss;
|
||||
unsigned int clkpost;
|
||||
unsigned int clkpre;
|
||||
unsigned int clkprepare;
|
||||
unsigned int clksettle;
|
||||
unsigned int clktermen;
|
||||
unsigned int clktrail;
|
||||
unsigned int clkzero;
|
||||
unsigned int dtermen;
|
||||
unsigned int eot;
|
||||
unsigned int hsexit;
|
||||
unsigned int hsprepare;
|
||||
unsigned int hszero;
|
||||
unsigned int hssettle;
|
||||
unsigned int hsskip;
|
||||
unsigned int hstrail;
|
||||
unsigned int init;
|
||||
unsigned int lpx;
|
||||
unsigned int taget;
|
||||
unsigned int tago;
|
||||
unsigned int tasure;
|
||||
unsigned int wakeup;
|
||||
};
|
||||
|
||||
struct inno_dsidphy {
|
||||
struct device *dev;
|
||||
struct clk *ref_clk;
|
||||
struct clk *pclk_phy;
|
||||
struct clk *pclk_host;
|
||||
void __iomem *phy_base;
|
||||
void __iomem *host_base;
|
||||
struct reset_control *rst;
|
||||
enum phy_mode mode;
|
||||
|
||||
struct {
|
||||
struct clk_hw hw;
|
||||
u8 prediv;
|
||||
u16 fbdiv;
|
||||
unsigned long rate;
|
||||
} pll;
|
||||
};
|
||||
|
||||
enum {
|
||||
REGISTER_PART_ANALOG,
|
||||
REGISTER_PART_DIGITAL,
|
||||
REGISTER_PART_CLOCK_LANE,
|
||||
REGISTER_PART_DATA0_LANE,
|
||||
REGISTER_PART_DATA1_LANE,
|
||||
REGISTER_PART_DATA2_LANE,
|
||||
REGISTER_PART_DATA3_LANE,
|
||||
REGISTER_PART_LVDS,
|
||||
};
|
||||
|
||||
static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct inno_dsidphy, pll.hw);
|
||||
}
|
||||
|
||||
static void phy_update_bits(struct inno_dsidphy *inno,
|
||||
u8 first, u8 second, u8 mask, u8 val)
|
||||
{
|
||||
u32 reg = PHY_REG(first, second) << 2;
|
||||
unsigned int tmp, orig;
|
||||
|
||||
orig = readl(inno->phy_base + reg);
|
||||
tmp = orig & ~mask;
|
||||
tmp |= val & mask;
|
||||
writel(tmp, inno->phy_base + reg);
|
||||
}
|
||||
|
||||
static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
|
||||
unsigned long period)
|
||||
{
|
||||
/* Global Operation Timing Parameters */
|
||||
timing->clkmiss = 0;
|
||||
timing->clkpost = 70000 + 52 * period;
|
||||
timing->clkpre = 8 * period;
|
||||
timing->clkprepare = 65000;
|
||||
timing->clksettle = 95000;
|
||||
timing->clktermen = 0;
|
||||
timing->clktrail = 80000;
|
||||
timing->clkzero = 260000;
|
||||
timing->dtermen = 0;
|
||||
timing->eot = 0;
|
||||
timing->hsexit = 120000;
|
||||
timing->hsprepare = 65000 + 4 * period;
|
||||
timing->hszero = 145000 + 6 * period;
|
||||
timing->hssettle = 85000 + 6 * period;
|
||||
timing->hsskip = 40000;
|
||||
timing->hstrail = max(8 * period, 60000 + 4 * period);
|
||||
timing->init = 100000000;
|
||||
timing->lpx = 60000;
|
||||
timing->taget = 5 * timing->lpx;
|
||||
timing->tago = 4 * timing->lpx;
|
||||
timing->tasure = 2 * timing->lpx;
|
||||
timing->wakeup = 1000000000;
|
||||
}
|
||||
|
||||
static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
|
||||
{
|
||||
struct mipi_dphy_timing gotp;
|
||||
const struct {
|
||||
unsigned long rate;
|
||||
u8 hs_prepare;
|
||||
u8 clk_lane_hs_zero;
|
||||
u8 data_lane_hs_zero;
|
||||
u8 hs_trail;
|
||||
} timings[] = {
|
||||
{ 110000000, 0x20, 0x16, 0x02, 0x22},
|
||||
{ 150000000, 0x06, 0x16, 0x03, 0x45},
|
||||
{ 200000000, 0x18, 0x17, 0x04, 0x0b},
|
||||
{ 250000000, 0x05, 0x17, 0x05, 0x16},
|
||||
{ 300000000, 0x51, 0x18, 0x06, 0x2c},
|
||||
{ 400000000, 0x64, 0x19, 0x07, 0x33},
|
||||
{ 500000000, 0x20, 0x1b, 0x07, 0x4e},
|
||||
{ 600000000, 0x6a, 0x1d, 0x08, 0x3a},
|
||||
{ 700000000, 0x3e, 0x1e, 0x08, 0x6a},
|
||||
{ 800000000, 0x21, 0x1f, 0x09, 0x29},
|
||||
{1000000000, 0x09, 0x20, 0x09, 0x27},
|
||||
};
|
||||
u32 t_txbyteclkhs, t_txclkesc, ui;
|
||||
u32 txbyteclkhs, txclkesc, esc_clk_div;
|
||||
u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
|
||||
u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
|
||||
unsigned int i;
|
||||
|
||||
/* Select MIPI mode */
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
|
||||
MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
|
||||
/* Configure PLL */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
|
||||
REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
|
||||
REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
|
||||
REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
|
||||
/* Enable PLL and LDO */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
|
||||
REG_LDOPD_MASK | REG_PLLPD_MASK,
|
||||
REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
|
||||
/* Reset analog */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
|
||||
REG_SYNCRST_MASK, REG_SYNCRST_RESET);
|
||||
udelay(1);
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
|
||||
REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
|
||||
/* Reset digital */
|
||||
phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
|
||||
REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
|
||||
udelay(1);
|
||||
phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
|
||||
REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
|
||||
|
||||
txbyteclkhs = inno->pll.rate / 8;
|
||||
t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
|
||||
|
||||
esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
|
||||
txclkesc = txbyteclkhs / esc_clk_div;
|
||||
t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
|
||||
|
||||
ui = div_u64(PSEC_PER_SEC, inno->pll.rate);
|
||||
|
||||
memset(&gotp, 0, sizeof(gotp));
|
||||
mipi_dphy_timing_get_default(&gotp, ui);
|
||||
|
||||
/*
|
||||
* The value of counter for HS Ths-exit
|
||||
* Ths-exit = Tpin_txbyteclkhs * value
|
||||
*/
|
||||
hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs);
|
||||
/*
|
||||
* The value of counter for HS Tclk-post
|
||||
* Tclk-post = Tpin_txbyteclkhs * value
|
||||
*/
|
||||
clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs);
|
||||
/*
|
||||
* The value of counter for HS Tclk-pre
|
||||
* Tclk-pre = Tpin_txbyteclkhs * value
|
||||
*/
|
||||
clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs);
|
||||
|
||||
/*
|
||||
* The value of counter for HS Tlpx Time
|
||||
* Tlpx = Tpin_txbyteclkhs * (2 + value)
|
||||
*/
|
||||
lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
|
||||
if (lpx >= 2)
|
||||
lpx -= 2;
|
||||
|
||||
/*
|
||||
* The value of counter for HS Tta-go
|
||||
* Tta-go for turnaround
|
||||
* Tta-go = Ttxclkesc * value
|
||||
*/
|
||||
ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc);
|
||||
/*
|
||||
* The value of counter for HS Tta-sure
|
||||
* Tta-sure for turnaround
|
||||
* Tta-sure = Ttxclkesc * value
|
||||
*/
|
||||
ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc);
|
||||
/*
|
||||
* The value of counter for HS Tta-wait
|
||||
* Tta-wait for turnaround
|
||||
* Tta-wait = Ttxclkesc * value
|
||||
*/
|
||||
ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(timings); i++)
|
||||
if (inno->pll.rate <= timings[i].rate)
|
||||
break;
|
||||
|
||||
if (i == ARRAY_SIZE(timings))
|
||||
--i;
|
||||
|
||||
hs_prepare = timings[i].hs_prepare;
|
||||
hs_trail = timings[i].hs_trail;
|
||||
clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
|
||||
data_lane_hs_zero = timings[i].data_lane_hs_zero;
|
||||
wakeup = 0x3ff;
|
||||
|
||||
for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
|
||||
if (i == REGISTER_PART_CLOCK_LANE)
|
||||
hs_zero = clk_lane_hs_zero;
|
||||
else
|
||||
hs_zero = data_lane_hs_zero;
|
||||
|
||||
phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
|
||||
T_LPX_CNT(lpx));
|
||||
phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
|
||||
T_HS_PREPARE_CNT(hs_prepare));
|
||||
phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
|
||||
T_HS_ZERO_CNT(hs_zero));
|
||||
phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
|
||||
T_HS_TRAIL_CNT(hs_trail));
|
||||
phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
|
||||
T_HS_EXIT_CNT(hs_exit));
|
||||
phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
|
||||
T_CLK_POST_CNT(clk_post));
|
||||
phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
|
||||
T_CLK_PRE_CNT(clk_pre));
|
||||
phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
|
||||
T_WAKEUP_CNT_HI(wakeup >> 8));
|
||||
phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
|
||||
T_WAKEUP_CNT_LO(wakeup));
|
||||
phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
|
||||
T_TA_GO_CNT(ta_go));
|
||||
phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
|
||||
T_TA_SURE_CNT(ta_sure));
|
||||
phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
|
||||
T_TA_WAIT_CNT(ta_wait));
|
||||
}
|
||||
|
||||
/* Enable all lanes on analog part */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
|
||||
LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
|
||||
LANE_EN_1 | LANE_EN_0);
|
||||
}
|
||||
|
||||
static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
|
||||
{
|
||||
u8 prediv = 2;
|
||||
u16 fbdiv = 28;
|
||||
|
||||
/* Sample clock reverse direction */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
|
||||
SAMPLE_CLOCK_DIRECTION_MASK,
|
||||
SAMPLE_CLOCK_DIRECTION_REVERSE);
|
||||
|
||||
/* Select LVDS mode */
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
|
||||
MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
|
||||
/* Configure PLL */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
|
||||
REG_PREDIV_MASK, REG_PREDIV(prediv));
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
|
||||
REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv));
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
|
||||
REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
|
||||
/* Enable PLL and Bandgap */
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
|
||||
LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
|
||||
LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
|
||||
|
||||
msleep(20);
|
||||
|
||||
/* Reset LVDS digital logic */
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
|
||||
LVDS_DIGITAL_INTERNAL_RESET_MASK,
|
||||
LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
|
||||
udelay(1);
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
|
||||
LVDS_DIGITAL_INTERNAL_RESET_MASK,
|
||||
LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
|
||||
/* Enable LVDS digital logic */
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
|
||||
LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
|
||||
LVDS_DIGITAL_INTERNAL_ENABLE);
|
||||
/* Enable LVDS analog driver */
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
|
||||
LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
|
||||
LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
|
||||
LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
|
||||
}
|
||||
|
||||
static int inno_dsidphy_power_on(struct phy *phy)
|
||||
{
|
||||
struct inno_dsidphy *inno = phy_get_drvdata(phy);
|
||||
|
||||
clk_prepare_enable(inno->pclk_phy);
|
||||
pm_runtime_get_sync(inno->dev);
|
||||
|
||||
/* Bandgap power on */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
|
||||
BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
|
||||
/* Enable power work */
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
|
||||
POWER_WORK_MASK, POWER_WORK_ENABLE);
|
||||
|
||||
switch (inno->mode) {
|
||||
case PHY_MODE_MIPI_DPHY:
|
||||
inno_dsidphy_mipi_mode_enable(inno);
|
||||
break;
|
||||
case PHY_MODE_LVDS:
|
||||
inno_dsidphy_lvds_mode_enable(inno);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int inno_dsidphy_power_off(struct phy *phy)
|
||||
{
|
||||
struct inno_dsidphy *inno = phy_get_drvdata(phy);
|
||||
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
|
||||
REG_LDOPD_MASK | REG_PLLPD_MASK,
|
||||
REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
|
||||
POWER_WORK_MASK, POWER_WORK_DISABLE);
|
||||
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
|
||||
BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
|
||||
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
|
||||
LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
|
||||
LVDS_DIGITAL_INTERNAL_DISABLE);
|
||||
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
|
||||
LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
|
||||
LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
|
||||
|
||||
pm_runtime_put(inno->dev);
|
||||
clk_disable_unprepare(inno->pclk_phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode,
|
||||
int submode)
|
||||
{
|
||||
struct inno_dsidphy *inno = phy_get_drvdata(phy);
|
||||
|
||||
switch (mode) {
|
||||
case PHY_MODE_MIPI_DPHY:
|
||||
case PHY_MODE_LVDS:
|
||||
inno->mode = mode;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops inno_dsidphy_ops = {
|
||||
.set_mode = inno_dsidphy_set_mode,
|
||||
.power_on = inno_dsidphy_power_on,
|
||||
.power_off = inno_dsidphy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static unsigned long inno_dsidphy_pll_round_rate(struct inno_dsidphy *inno,
|
||||
unsigned long prate,
|
||||
unsigned long rate,
|
||||
u8 *prediv, u16 *fbdiv)
|
||||
{
|
||||
unsigned long best_freq = 0;
|
||||
unsigned long fref, fout;
|
||||
u8 min_prediv, max_prediv;
|
||||
u8 _prediv, best_prediv = 1;
|
||||
u16 _fbdiv, best_fbdiv = 1;
|
||||
u32 min_delta = UINT_MAX;
|
||||
|
||||
/*
|
||||
* The PLL output frequency can be calculated using a simple formula:
|
||||
* PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
|
||||
* PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
|
||||
*/
|
||||
fref = prate / 2;
|
||||
if (rate > 1000000000UL)
|
||||
fout = 1000000000UL;
|
||||
else
|
||||
fout = rate;
|
||||
|
||||
/* 5Mhz < Fref / prediv < 40MHz */
|
||||
min_prediv = DIV_ROUND_UP(fref, 40000000);
|
||||
max_prediv = fref / 5000000;
|
||||
|
||||
for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
|
||||
u64 tmp;
|
||||
u32 delta;
|
||||
|
||||
tmp = (u64)fout * _prediv;
|
||||
do_div(tmp, fref);
|
||||
_fbdiv = tmp;
|
||||
|
||||
/*
|
||||
* The possible settings of feedback divider are
|
||||
* 12, 13, 14, 16, ~ 511
|
||||
*/
|
||||
if (_fbdiv == 15)
|
||||
continue;
|
||||
|
||||
if (_fbdiv < 12 || _fbdiv > 511)
|
||||
continue;
|
||||
|
||||
tmp = (u64)_fbdiv * fref;
|
||||
do_div(tmp, _prediv);
|
||||
|
||||
delta = abs(fout - tmp);
|
||||
if (!delta) {
|
||||
best_prediv = _prediv;
|
||||
best_fbdiv = _fbdiv;
|
||||
best_freq = tmp;
|
||||
break;
|
||||
} else if (delta < min_delta) {
|
||||
best_prediv = _prediv;
|
||||
best_fbdiv = _fbdiv;
|
||||
best_freq = tmp;
|
||||
min_delta = delta;
|
||||
}
|
||||
}
|
||||
|
||||
if (best_freq) {
|
||||
*prediv = best_prediv;
|
||||
*fbdiv = best_fbdiv;
|
||||
}
|
||||
|
||||
return best_freq;
|
||||
}
|
||||
|
||||
static long inno_dsidphy_pll_clk_round_rate(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct inno_dsidphy *inno = hw_to_inno(hw);
|
||||
unsigned long fout;
|
||||
u16 fbdiv = 1;
|
||||
u8 prediv = 1;
|
||||
|
||||
fout = inno_dsidphy_pll_round_rate(inno, *prate, rate,
|
||||
&prediv, &fbdiv);
|
||||
|
||||
return fout;
|
||||
}
|
||||
|
||||
static int inno_dsidphy_pll_clk_set_rate(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct inno_dsidphy *inno = hw_to_inno(hw);
|
||||
unsigned long fout;
|
||||
u16 fbdiv = 1;
|
||||
u8 prediv = 1;
|
||||
|
||||
fout = inno_dsidphy_pll_round_rate(inno, parent_rate, rate,
|
||||
&prediv, &fbdiv);
|
||||
|
||||
dev_dbg(inno->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n",
|
||||
parent_rate, fout, prediv, fbdiv);
|
||||
|
||||
inno->pll.prediv = prediv;
|
||||
inno->pll.fbdiv = fbdiv;
|
||||
inno->pll.rate = fout;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
inno_dsidphy_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
|
||||
{
|
||||
struct inno_dsidphy *inno = hw_to_inno(hw);
|
||||
|
||||
/* PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 */
|
||||
return (prate / inno->pll.prediv * inno->pll.fbdiv) / 2;
|
||||
}
|
||||
|
||||
static const struct clk_ops inno_dsidphy_pll_clk_ops = {
|
||||
.round_rate = inno_dsidphy_pll_clk_round_rate,
|
||||
.set_rate = inno_dsidphy_pll_clk_set_rate,
|
||||
.recalc_rate = inno_dsidphy_pll_clk_recalc_rate,
|
||||
};
|
||||
|
||||
static int inno_dsidphy_pll_register(struct inno_dsidphy *inno)
|
||||
{
|
||||
struct device *dev = inno->dev;
|
||||
struct clk *clk;
|
||||
const char *parent_name;
|
||||
struct clk_init_data init;
|
||||
int ret;
|
||||
|
||||
parent_name = __clk_get_name(inno->ref_clk);
|
||||
|
||||
init.name = "mipi_dphy_pll";
|
||||
ret = of_property_read_string(dev->of_node, "clock-output-names",
|
||||
&init.name);
|
||||
if (ret < 0)
|
||||
dev_dbg(dev, "phy should set clock-output-names property\n");
|
||||
|
||||
init.ops = &inno_dsidphy_pll_clk_ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = 0;
|
||||
|
||||
inno->pll.hw.init = &init;
|
||||
clk = devm_clk_register(dev, &inno->pll.hw);
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
dev_err(dev, "failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
|
||||
&inno->pll.hw);
|
||||
}
|
||||
|
||||
static int inno_dsidphy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct inno_dsidphy *inno;
|
||||
struct phy_provider *phy_provider;
|
||||
struct phy *phy;
|
||||
int ret;
|
||||
|
||||
inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
|
||||
if (!inno)
|
||||
return -ENOMEM;
|
||||
|
||||
inno->dev = dev;
|
||||
platform_set_drvdata(pdev, inno);
|
||||
|
||||
inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (!inno->phy_base)
|
||||
return -ENOMEM;
|
||||
|
||||
inno->ref_clk = devm_clk_get(dev, "ref");
|
||||
if (IS_ERR(inno->ref_clk)) {
|
||||
ret = PTR_ERR(inno->ref_clk);
|
||||
dev_err(dev, "failed to get ref clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
inno->pclk_phy = devm_clk_get(dev, "pclk");
|
||||
if (IS_ERR(inno->pclk_phy)) {
|
||||
ret = PTR_ERR(inno->pclk_phy);
|
||||
dev_err(dev, "failed to get phy pclk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
inno->rst = devm_reset_control_get(dev, "apb");
|
||||
if (IS_ERR(inno->rst)) {
|
||||
ret = PTR_ERR(inno->rst);
|
||||
dev_err(dev, "failed to get system reset control: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
ret = PTR_ERR(phy);
|
||||
dev_err(dev, "failed to create phy: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy_set_drvdata(phy, inno);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
ret = PTR_ERR(phy_provider);
|
||||
dev_err(dev, "failed to register phy provider: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = inno_dsidphy_pll_register(inno);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int inno_dsidphy_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct inno_dsidphy *inno = platform_get_drvdata(pdev);
|
||||
|
||||
pm_runtime_disable(inno->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id inno_dsidphy_of_match[] = {
|
||||
{ .compatible = "rockchip,px30-dsi-dphy", },
|
||||
{ .compatible = "rockchip,rk3128-dsi-dphy", },
|
||||
{ .compatible = "rockchip,rk3368-dsi-dphy", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match);
|
||||
|
||||
static struct platform_driver inno_dsidphy_driver = {
|
||||
.driver = {
|
||||
.name = "inno-dsidphy",
|
||||
.of_match_table = of_match_ptr(inno_dsidphy_of_match),
|
||||
},
|
||||
.probe = inno_dsidphy_probe,
|
||||
.remove = inno_dsidphy_remove,
|
||||
};
|
||||
module_platform_driver(inno_dsidphy_driver);
|
||||
|
||||
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -1423,6 +1423,7 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
|
||||
{ .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
|
||||
|
||||
@ -857,9 +857,32 @@ static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
|
||||
{
|
||||
}
|
||||
|
||||
static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
|
||||
bool status)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
|
||||
|
||||
value = padctl_readl(padctl, USB2_VBUS_ID);
|
||||
|
||||
if (status) {
|
||||
value |= VBUS_OVERRIDE;
|
||||
value &= ~ID_OVERRIDE(~0);
|
||||
value |= ID_OVERRIDE_FLOATING;
|
||||
} else {
|
||||
value &= ~VBUS_OVERRIDE;
|
||||
}
|
||||
|
||||
padctl_writel(padctl, value, USB2_VBUS_ID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
|
||||
.probe = tegra186_xusb_padctl_probe,
|
||||
.remove = tegra186_xusb_padctl_remove,
|
||||
.vbus_override = tegra186_xusb_padctl_vbus_override,
|
||||
};
|
||||
|
||||
static const char * const tegra186_xusb_padctl_supply_names[] = {
|
||||
|
||||
@ -39,7 +39,10 @@
|
||||
#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
|
||||
|
||||
#define XUSB_PADCTL_USB2_PORT_CAP 0x008
|
||||
#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
|
||||
#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
|
||||
#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
|
||||
#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
|
||||
#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
|
||||
|
||||
#define XUSB_PADCTL_SS_PORT_MAP 0x014
|
||||
@ -47,6 +50,7 @@
|
||||
#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5)
|
||||
#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
|
||||
#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
|
||||
#define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
|
||||
|
||||
#define XUSB_PADCTL_ELPG_PROGRAM1 0x024
|
||||
#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
|
||||
@ -61,9 +65,14 @@
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
|
||||
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP (1 << 18)
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN (1 << 22)
|
||||
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
|
||||
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
|
||||
|
||||
#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
|
||||
@ -222,6 +231,12 @@
|
||||
#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
|
||||
#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
|
||||
|
||||
#define XUSB_PADCTL_USB2_VBUS_ID 0xc60
|
||||
#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON (1 << 14)
|
||||
#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT 18
|
||||
#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf
|
||||
#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8
|
||||
|
||||
struct tegra210_xusb_fuse_calibration {
|
||||
u32 hs_curr_level[4];
|
||||
u32 hs_term_range_adj;
|
||||
@ -940,6 +955,34 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
|
||||
|
||||
priv = to_tegra210_xusb_padctl(padctl);
|
||||
|
||||
if (port->usb3_port_fake != -1) {
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
|
||||
value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
|
||||
port->usb3_port_fake);
|
||||
value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(
|
||||
port->usb3_port_fake, index);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
|
||||
port->usb3_port_fake);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
|
||||
usleep_range(100, 200);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
|
||||
port->usb3_port_fake);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
|
||||
usleep_range(100, 200);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
|
||||
port->usb3_port_fake);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
}
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
|
||||
value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<
|
||||
XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |
|
||||
@ -957,7 +1000,14 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
|
||||
value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);
|
||||
value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
|
||||
if (port->mode == USB_DR_MODE_UNKNOWN)
|
||||
value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index);
|
||||
else if (port->mode == USB_DR_MODE_PERIPHERAL)
|
||||
value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index);
|
||||
else if (port->mode == USB_DR_MODE_HOST)
|
||||
value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
|
||||
else if (port->mode == USB_DR_MODE_OTG)
|
||||
value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
|
||||
@ -989,7 +1039,12 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
|
||||
XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
|
||||
value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK <<
|
||||
XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT);
|
||||
value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
|
||||
if (port->mode == USB_DR_MODE_HOST)
|
||||
value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
|
||||
else
|
||||
value |=
|
||||
XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL <<
|
||||
XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT;
|
||||
padctl_writel(padctl, value,
|
||||
XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
|
||||
|
||||
@ -1062,6 +1117,32 @@ static int tegra210_usb2_phy_power_off(struct phy *phy)
|
||||
|
||||
mutex_lock(&padctl->lock);
|
||||
|
||||
if (port->usb3_port_fake != -1) {
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
|
||||
port->usb3_port_fake);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
|
||||
usleep_range(100, 200);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
|
||||
port->usb3_port_fake);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
|
||||
usleep_range(250, 350);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
|
||||
port->usb3_port_fake);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
|
||||
value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake,
|
||||
XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED);
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
|
||||
}
|
||||
|
||||
if (WARN_ON(pad->enable == 0))
|
||||
goto out;
|
||||
|
||||
@ -1225,13 +1306,10 @@ static int tegra210_hsic_phy_power_on(struct phy *phy)
|
||||
struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
|
||||
struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
|
||||
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
|
||||
struct tegra210_xusb_padctl *priv;
|
||||
unsigned int index = lane->index;
|
||||
u32 value;
|
||||
int err;
|
||||
|
||||
priv = to_tegra210_xusb_padctl(padctl);
|
||||
|
||||
err = regulator_enable(pad->supply);
|
||||
if (err)
|
||||
return err;
|
||||
@ -1945,6 +2023,52 @@ static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {
|
||||
.map = tegra210_usb3_port_map,
|
||||
};
|
||||
|
||||
static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
|
||||
bool status)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
|
||||
|
||||
if (status) {
|
||||
value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
|
||||
value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
|
||||
XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
|
||||
value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
|
||||
XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
|
||||
} else {
|
||||
value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
|
||||
}
|
||||
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra210_utmi_port_reset(struct phy *phy)
|
||||
{
|
||||
struct tegra_xusb_padctl *padctl;
|
||||
struct tegra_xusb_lane *lane;
|
||||
u32 value;
|
||||
|
||||
lane = phy_get_drvdata(phy);
|
||||
padctl = lane->pad->padctl;
|
||||
|
||||
value = padctl_readl(padctl,
|
||||
XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index));
|
||||
|
||||
if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) ||
|
||||
(value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) {
|
||||
tegra210_xusb_padctl_vbus_override(padctl, false);
|
||||
tegra210_xusb_padctl_vbus_override(padctl, true);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)
|
||||
{
|
||||
@ -2007,6 +2131,8 @@ static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
|
||||
.remove = tegra210_xusb_padctl_remove,
|
||||
.usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect,
|
||||
.hsic_set_idle = tegra210_hsic_set_idle,
|
||||
.vbus_override = tegra210_xusb_padctl_vbus_override,
|
||||
.utmi_port_reset = tegra210_utmi_port_reset,
|
||||
};
|
||||
|
||||
static const char * const tegra210_xusb_padctl_supply_names[] = {
|
||||
@ -2036,6 +2162,7 @@ const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {
|
||||
.ops = &tegra210_xusb_padctl_ops,
|
||||
.supply_names = tegra210_xusb_padctl_supply_names,
|
||||
.num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names),
|
||||
.need_fake_usb3_port = true,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);
|
||||
|
||||
|
||||
@ -800,9 +800,62 @@ static void __tegra_xusb_remove_ports(struct tegra_xusb_padctl *padctl)
|
||||
}
|
||||
}
|
||||
|
||||
static int tegra_xusb_find_unused_usb3_port(struct tegra_xusb_padctl *padctl)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < padctl->soc->ports.usb3.count; i++) {
|
||||
np = tegra_xusb_find_port_node(padctl, "usb3", i);
|
||||
if (!np || !of_device_is_available(np))
|
||||
return i;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static bool tegra_xusb_port_is_companion(struct tegra_xusb_usb2_port *usb2)
|
||||
{
|
||||
unsigned int i;
|
||||
struct tegra_xusb_usb3_port *usb3;
|
||||
struct tegra_xusb_padctl *padctl = usb2->base.padctl;
|
||||
|
||||
for (i = 0; i < padctl->soc->ports.usb3.count; i++) {
|
||||
usb3 = tegra_xusb_find_usb3_port(padctl, i);
|
||||
if (usb3 && usb3->port == usb2->base.index)
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int tegra_xusb_update_usb3_fake_port(struct tegra_xusb_usb2_port *usb2)
|
||||
{
|
||||
int fake;
|
||||
|
||||
/* Disable usb3_port_fake usage by default and assign if needed */
|
||||
usb2->usb3_port_fake = -1;
|
||||
|
||||
if ((usb2->mode == USB_DR_MODE_OTG ||
|
||||
usb2->mode == USB_DR_MODE_PERIPHERAL) &&
|
||||
!tegra_xusb_port_is_companion(usb2)) {
|
||||
fake = tegra_xusb_find_unused_usb3_port(usb2->base.padctl);
|
||||
if (fake < 0) {
|
||||
dev_err(&usb2->base.dev, "no unused USB3 ports available\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dev_dbg(&usb2->base.dev, "Found unused usb3 port: %d\n", fake);
|
||||
usb2->usb3_port_fake = fake;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_xusb_setup_ports(struct tegra_xusb_padctl *padctl)
|
||||
{
|
||||
struct tegra_xusb_port *port;
|
||||
struct tegra_xusb_usb2_port *usb2;
|
||||
unsigned int i;
|
||||
int err = 0;
|
||||
|
||||
@ -832,6 +885,18 @@ static int tegra_xusb_setup_ports(struct tegra_xusb_padctl *padctl)
|
||||
goto remove_ports;
|
||||
}
|
||||
|
||||
if (padctl->soc->need_fake_usb3_port) {
|
||||
for (i = 0; i < padctl->soc->ports.usb2.count; i++) {
|
||||
usb2 = tegra_xusb_find_usb2_port(padctl, i);
|
||||
if (!usb2)
|
||||
continue;
|
||||
|
||||
err = tegra_xusb_update_usb3_fake_port(usb2);
|
||||
if (err < 0)
|
||||
goto remove_ports;
|
||||
}
|
||||
}
|
||||
|
||||
list_for_each_entry(port, &padctl->ports, list) {
|
||||
err = port->ops->enable(port);
|
||||
if (err < 0)
|
||||
@ -862,7 +927,6 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev)
|
||||
struct tegra_xusb_padctl *padctl;
|
||||
const struct of_device_id *match;
|
||||
struct resource *res;
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
/* for backwards compatibility with old device trees */
|
||||
@ -907,8 +971,9 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev)
|
||||
goto remove;
|
||||
}
|
||||
|
||||
for (i = 0; i < padctl->soc->num_supplies; i++)
|
||||
padctl->supplies[i].supply = padctl->soc->supply_names[i];
|
||||
regulator_bulk_set_supply_names(padctl->supplies,
|
||||
padctl->soc->supply_names,
|
||||
padctl->soc->num_supplies);
|
||||
|
||||
err = devm_regulator_bulk_get(&pdev->dev, padctl->soc->num_supplies,
|
||||
padctl->supplies);
|
||||
@ -1056,6 +1121,28 @@ int tegra_xusb_padctl_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_xusb_padctl_usb3_set_lfps_detect);
|
||||
|
||||
int tegra_xusb_padctl_set_vbus_override(struct tegra_xusb_padctl *padctl,
|
||||
bool val)
|
||||
{
|
||||
if (padctl->soc->ops->vbus_override)
|
||||
return padctl->soc->ops->vbus_override(padctl, val);
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_xusb_padctl_set_vbus_override);
|
||||
|
||||
int tegra_phy_xusb_utmi_port_reset(struct phy *phy)
|
||||
{
|
||||
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
|
||||
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
|
||||
|
||||
if (padctl->soc->ops->utmi_port_reset)
|
||||
return padctl->soc->ops->utmi_port_reset(phy);
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_phy_xusb_utmi_port_reset);
|
||||
|
||||
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Tegra XUSB Pad Controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -291,6 +291,7 @@ struct tegra_xusb_usb2_port {
|
||||
struct regulator *supply;
|
||||
enum usb_dr_mode mode;
|
||||
bool internal;
|
||||
int usb3_port_fake;
|
||||
};
|
||||
|
||||
static inline struct tegra_xusb_usb2_port *
|
||||
@ -372,6 +373,8 @@ struct tegra_xusb_padctl_ops {
|
||||
unsigned int index, bool idle);
|
||||
int (*usb3_set_lfps_detect)(struct tegra_xusb_padctl *padctl,
|
||||
unsigned int index, bool enable);
|
||||
int (*vbus_override)(struct tegra_xusb_padctl *padctl, bool set);
|
||||
int (*utmi_port_reset)(struct phy *phy);
|
||||
};
|
||||
|
||||
struct tegra_xusb_padctl_soc {
|
||||
@ -389,6 +392,7 @@ struct tegra_xusb_padctl_soc {
|
||||
|
||||
const char * const *supply_names;
|
||||
unsigned int num_supplies;
|
||||
bool need_fake_usb3_port;
|
||||
};
|
||||
|
||||
struct tegra_xusb_padctl {
|
||||
|
||||
@ -189,7 +189,6 @@ static int dm816x_usb_phy_probe(struct platform_device *pdev)
|
||||
struct phy_provider *phy_provider;
|
||||
struct usb_otg *otg;
|
||||
const struct of_device_id *of_id;
|
||||
const struct usb_phy_data *phy_data;
|
||||
int error;
|
||||
|
||||
of_id = of_match_device(of_match_ptr(dm816x_usb_phy_id_table),
|
||||
@ -220,8 +219,6 @@ static int dm816x_usb_phy_probe(struct platform_device *pdev)
|
||||
if (phy->usbphy_ctrl == 0x2c)
|
||||
phy->instance = 1;
|
||||
|
||||
phy_data = of_id->data;
|
||||
|
||||
otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
|
||||
if (!otg)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -69,11 +69,11 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
|
||||
rgmii_id = 1;
|
||||
|
||||
@ -38,7 +38,8 @@ enum phy_mode {
|
||||
PHY_MODE_PCIE,
|
||||
PHY_MODE_ETHERNET,
|
||||
PHY_MODE_MIPI_DPHY,
|
||||
PHY_MODE_SATA
|
||||
PHY_MODE_SATA,
|
||||
PHY_MODE_LVDS,
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@ -18,5 +18,7 @@ int tegra_xusb_padctl_hsic_set_idle(struct tegra_xusb_padctl *padctl,
|
||||
unsigned int port, bool idle);
|
||||
int tegra_xusb_padctl_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
|
||||
unsigned int port, bool enable);
|
||||
|
||||
int tegra_xusb_padctl_set_vbus_override(struct tegra_xusb_padctl *padctl,
|
||||
bool val);
|
||||
int tegra_phy_xusb_utmi_port_reset(struct phy *phy);
|
||||
#endif /* PHY_TEGRA_XUSB_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user